
tests=2000

e=11
f=52
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=11
f=53
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=11
f=54
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=11
f=60
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=11
f=51
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=11
f=49
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=11
f=20
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd


e=10
f=52
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=10
f=53
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=10
f=54
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=10
f=60
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=10
f=51
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=10
f=49
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=10
f=20
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd


e=9
f=52
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=9
f=53
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=9
f=54
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=9
f=60
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=9
f=51
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=9
f=49
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=9
f=20
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd



e=8
f=52
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=8
f=53
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=8
f=54
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=8
f=60
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=8
f=51
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=8
f=49
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

e=8
f=20
cd /home/fdedinec/Boulot/Recherche/Hard/FloPoCo.bibine/trunk
./flopoco InputIEEE 11 52 $e $f TestBench $tests  
 mv flopoco.vhdl ghdl
cd ghdl
echo
echo Testing $e $f
   ghdl -a --ieee=synopsys -fexplicit flopoco.vhdl
   ghdl -e --ieee=synopsys -fexplicit TestBench_InputIEEE_11_52_to_$e'_'$f
   ghdl -r --ieee=synopsys TestBench_InputIEEE_11_52_to_$e'_'$f --vcd=TestBench_InputIEEE_11_52_to_$e'_'$f.vcd

