--------------------------------------------------------------------------------
-- MC6809 CPU
--------------------------------------------------------------------------------
-- DO 8/2017
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


USE std.textio.ALL;

LIBRARY work;
USE work.base_pack.ALL;
USE work.mc6809_pack.ALL;

ENTITY tbvec IS

END ENTITY tbvec;


ARCHITECTURE sim OF tbvec IS
  COMPONENT vec_core IS
    PORT (
      sound             : OUT unsigned(15 DOWNTO 0);
      left_udlr         : IN  uv4;
      left_x            : IN  uv8;
      left_y            : IN  uv8;
      right_udlr        : IN  uv4;
      right_x           : IN  uv8;
      right_y           : IN  uv8;
      pause             : IN  std_logic;
      vga_r             : OUT uv8;
      vga_g             : OUT uv8;
      vga_b             : OUT uv8;
      vga_de            : OUT std_logic;
      vga_hsyn          : OUT std_logic;
      vga_vsyn          : OUT std_logic;
      vga_hpos          : OUT uint12;
      vga_vpos          : OUT uint12;
      vga_clk           : IN  std_logic;
      vga_en            : IN  std_logic;
      spot_x            : OUT uv16;
      spot_y            : OUT uv16;
      spot_z            : OUT uv8;
      spot_en           : OUT std_logic;
      status            : IN  uv32;
      avl_clk           : OUT std_logic;
      avl_waitrequest   : IN  std_logic;
      avl_readdata      : IN  std_logic_vector(31 DOWNTO 0);
      avl_readdatavalid : IN  std_logic;
      avl_burstcount    : OUT std_logic_vector(7 DOWNTO 0);
      avl_writedata     : OUT std_logic_vector(31 DOWNTO 0);
      avl_address       : OUT std_logic_vector(29 DOWNTO 0);
      avl_write         : OUT std_logic;
      avl_read          : OUT std_logic;
      avl_byteenable    : OUT std_logic_vector(3 DOWNTO 0);
      vid_clk           : OUT std_logic;
      vid_waitrequest   : IN  std_logic;
      vid_readdata      : IN  std_logic_vector(31 DOWNTO 0);
      vid_readdatavalid : IN  std_logic;
      vid_burstcount    : OUT std_logic_vector(7 DOWNTO 0);
      vid_writedata     : OUT std_logic_vector(31 DOWNTO 0);
      vid_address       : OUT std_logic_vector(29 DOWNTO 0);
      vid_write         : OUT std_logic;
      vid_read          : OUT std_logic;
      vid_byteenable    : OUT std_logic_vector(3 DOWNTO 0);
      rom_clk           : OUT std_logic;
      rom_waitrequest   : IN  std_logic;
      rom_readdata      : IN  std_logic_vector(31 DOWNTO 0);
      rom_readdatavalid : IN  std_logic;
      rom_burstcount    : OUT std_logic_vector(7 DOWNTO 0);
      rom_writedata     : OUT std_logic_vector(31 DOWNTO 0);
      rom_address       : OUT std_logic_vector(29 DOWNTO 0);
      rom_write         : OUT std_logic;
      rom_read          : OUT std_logic;
      rom_byteenable    : OUT std_logic_vector(3 DOWNTO 0);
      host_download     : IN  std_logic;
      host_wr           : IN  std_logic;
      host_addr         : IN  std_logic_vector(24 DOWNTO 0);
      host_data         : IN  std_logic_vector(15 DOWNTO 0);
      host_wait         : OUT std_logic;
      clksys            : IN  std_logic;
      reset_na          : IN  std_logic);
  END COMPONENT vec_core;
  
  SIGNAL sound      : unsigned(15 DOWNTO 0);
  SIGNAL left_udlr  : uv4 :=x"0";
  SIGNAL left_x     : uv8 :=x"00";
  SIGNAL left_y     : uv8 :=x"00";
  SIGNAL right_udlr : uv4 :=x"0";
  SIGNAL right_x    : uv8 :=x"00";
  SIGNAL right_y    : uv8 :=x"00";
  SIGNAL clksys     : std_logic :='0';
  SIGNAL reset_na   : std_logic;

  SIGNAL vga_r    : uv8;
  SIGNAL vga_g    : uv8;
  SIGNAL vga_b    : uv8;
  SIGNAL vga_de   : std_logic;
  SIGNAL vga_hsyn : std_logic;
  SIGNAL vga_vsyn : std_logic;
  SIGNAL vga_hpos : uint12;
  SIGNAL vga_vpos : uint12;
  SIGNAL vga_clk  : std_logic;
  SIGNAL vga_en   : std_logic :='1';

  SIGNAL spot_x : uv16;
  SIGNAL spot_y : uv16;
  SIGNAL spot_z : uv8;
  SIGNAL spot_en : std_logic;

  SIGNAL status : uv32;

  SIGNAL pause : std_logic;
  
  SIGNAL avl_clk           : std_logic;
  SIGNAL avl_waitrequest   : std_logic;
  SIGNAL avl_readdata      : std_logic_vector(31 DOWNTO 0);
  SIGNAL avl_readdatavalid : std_logic;
  SIGNAL avl_burstcount    : std_logic_vector(7 DOWNTO 0);
  SIGNAL avl_writedata     : std_logic_vector(31 DOWNTO 0);
  SIGNAL avl_address       : std_logic_vector(29 DOWNTO 0);
  SIGNAL avl_write         : std_logic;
  SIGNAL avl_read          : std_logic;
  SIGNAL avl_byteenable    : std_logic_vector(3 DOWNTO 0);

  SIGNAL vid_clk           : std_logic;
  SIGNAL vid_waitrequest   : std_logic;
  SIGNAL vid_readdata      : std_logic_vector(31 DOWNTO 0);
  SIGNAL vid_readdatavalid : std_logic;
  SIGNAL vid_burstcount    : std_logic_vector(7 DOWNTO 0);
  SIGNAL vid_writedata     : std_logic_vector(31 DOWNTO 0);
  SIGNAL vid_address       : std_logic_vector(29 DOWNTO 0);
  SIGNAL vid_write         : std_logic;
  SIGNAL vid_read          : std_logic;
  SIGNAL vid_byteenable    : std_logic_vector(3 DOWNTO 0);

  SIGNAL rom_clk           : std_logic;
  SIGNAL rom_waitrequest   : std_logic;
  SIGNAL rom_readdata      : std_logic_vector(31 DOWNTO 0);
  SIGNAL rom_readdatavalid : std_logic;
  SIGNAL rom_burstcount    : std_logic_vector(7 DOWNTO 0);
  SIGNAL rom_writedata     : std_logic_vector(31 DOWNTO 0);
  SIGNAL rom_address       : std_logic_vector(29 DOWNTO 0);
  SIGNAL rom_write         : std_logic;
  SIGNAL rom_read          : std_logic;
  SIGNAL rom_byteenable    : std_logic_vector(3 DOWNTO 0);

  SIGNAL host_download : std_logic;
  SIGNAL host_wr       : std_logic;
  SIGNAL host_addr     : std_logic_vector(24 DOWNTO 0);
  SIGNAL host_data     : std_logic_vector(15 DOWNTO 0);
  SIGNAL host_wait     : std_logic;

  SHARED VARIABLE mem : arr_uv32(0 TO 2**21-1) :=(OTHERS =>x"00000000");
  
  SHARED VARIABLE rom : arr_uv32(0 TO 2**21-1) :=(OTHERS =>x"00000000");
  
  FILE fil : text OPEN write_mode IS "graph.log";


  CONSTANT cart : arr_uv8 := (
    x"67",x"20",x"47",x"43",x"45",x"20",x"31",x"39"  ,x"39",x"38",x"80",x"fe",x"c6",x"f8",x"50",x"20",
    x"c8",x"56",x"45",x"43",x"54",x"52",x"45",x"58"  ,x"20",x"50",x"4f",x"4e",x"47",x"80",x"f8",x"50",
    x"00",x"90",x"67",x"20",x"43",x"48",x"52",x"49"  ,x"53",x"54",x"4f",x"50",x"48",x"45",x"52",x"20",
    x"53",x"41",x"4c",x"4f",x"4d",x"4f",x"4e",x"80"  ,x"00",x"bd",x"03",x"f6",x"bd",x"03",x"95",x"bd",
    x"04",x"38",x"bd",x"f1",x"92",x"bd",x"f2",x"89"  ,x"bd",x"01",x"72",x"bd",x"01",x"2a",x"bd",x"01",
    x"a0",x"bd",x"04",x"2b",x"b6",x"c9",x"3b",x"81"  ,x"30",x"27",x"02",x"20",x"e2",x"4f",x"b7",x"c8",
    x"a7",x"b7",x"c8",x"a9",x"b7",x"c8",x"a8",x"b7"  ,x"c8",x"aa",x"b7",x"c8",x"ab",x"86",x"01",x"b7",
    x"c8",x"56",x"ce",x"ff",x"62",x"ff",x"c8",x"90"  ,x"bd",x"04",x"38",x"bd",x"f1",x"92",x"bd",x"f2",
    x"89",x"b6",x"c8",x"a8",x"f6",x"c8",x"a9",x"fd"  ,x"c8",x"2a",x"b6",x"c8",x"a7",x"bd",x"f2",x"ab",
    x"b6",x"c8",x"aa",x"f6",x"c8",x"ab",x"ce",x"04"  ,x"4f",x"bd",x"f3",x"7a",x"b6",x"c8",x"a7",x"8b",
    x"03",x"b7",x"c8",x"a7",x"84",x"01",x"27",x"08"  ,x"b6",x"c8",x"a8",x"80",x"01",x"b7",x"c8",x"a8",
    x"b6",x"c8",x"aa",x"8b",x"02",x"81",x"70",x"25"  ,x"02",x"86",x"70",x"b7",x"c8",x"aa",x"b6",x"c8",
    x"ab",x"80",x"02",x"81",x"90",x"2c",x"02",x"86"  ,x"90",x"b7",x"c8",x"ab",x"b6",x"c8",x"a9",x"8b",
    x"03",x"b7",x"c8",x"a9",x"b6",x"c8",x"a7",x"81"  ,x"7f",x"25",x"9d",x"bd",x"f1",x"ba",x"b6",x"c8",
    x"a9",x"80",x"03",x"b7",x"c8",x"a9",x"bd",x"04"  ,x"38",x"bd",x"f1",x"92",x"bd",x"f2",x"89",x"bd",
    x"f2",x"a9",x"cc",x"fb",x"30",x"fd",x"c8",x"2a"  ,x"86",x"e0",x"c6",x"d0",x"ce",x"c9",x"14",x"bd",
    x"f3",x"7a",x"b6",x"c8",x"a8",x"f6",x"c8",x"a9"  ,x"fd",x"c8",x"2a",x"b6",x"c8",x"aa",x"f6",x"c8",
    x"ab",x"ce",x"04",x"4f",x"bd",x"f3",x"7a",x"bd"  ,x"f1",x"ba",x"81",x"00",x"27",x"c8",x"ce",x"cb",
    x"eb",x"8e",x"c9",x"1a",x"bd",x"f8",x"d8",x"7e"  ,x"00",x"39",x"bd",x"f1",x"f8",x"f6",x"c8",x"93",
    x"b6",x"c8",x"1b",x"27",x"2a",x"2b",x"15",x"c1"  ,x"5b",x"27",x"24",x"fb",x"c8",x"95",x"f7",x"c8",
    x"93",x"c1",x"5b",x"2f",x"1a",x"c6",x"5b",x"f7"  ,x"c8",x"93",x"20",x"13",x"c1",x"91",x"27",x"0f",
    x"f0",x"c8",x"95",x"f7",x"c8",x"93",x"c1",x"91"  ,x"2c",x"05",x"c6",x"91",x"f7",x"c8",x"93",x"fc",
    x"c8",x"92",x"bd",x"f3",x"12",x"b6",x"c8",x"a3"  ,x"bd",x"f2",x"ab",x"8e",x"c9",x"3e",x"bd",x"f3",
    x"d6",x"39",x"b6",x"c8",x"a4",x"bd",x"f2",x"ab"  ,x"b6",x"c8",x"a2",x"b7",x"d0",x"04",x"cc",x"90",
    x"90",x"bd",x"f3",x"12",x"8e",x"c9",x"48",x"bd"  ,x"f3",x"d6",x"cc",x"ff",x"90",x"bd",x"f3",x"12",
    x"b6",x"c8",x"a2",x"b7",x"d0",x"04",x"c6",x"90"  ,x"50",x"86",x"90",x"40",x"bd",x"f3",x"12",x"39",
    x"b6",x"c8",x"9e",x"81",x"00",x"26",x"03",x"bd"  ,x"03",x"0c",x"b6",x"c8",x"9a",x"27",x"06",x"4a",
    x"b7",x"c8",x"9a",x"20",x"0f",x"f6",x"c8",x"96"  ,x"fb",x"c8",x"98",x"f7",x"c8",x"96",x"b6",x"c8",
    x"9c",x"b7",x"c8",x"9a",x"b6",x"c8",x"9b",x"27"  ,x"06",x"4a",x"b7",x"c8",x"9b",x"20",x"0f",x"f6",
    x"c8",x"97",x"fb",x"c8",x"99",x"f7",x"c8",x"97"  ,x"b6",x"c8",x"9d",x"b7",x"c8",x"9b",x"b6",x"c8",
    x"99",x"2b",x"12",x"c1",x"6a",x"2f",x"20",x"70"  ,x"c8",x"99",x"86",x"01",x"b7",x"c8",x"56",x"ce",
    x"04",x"6a",x"ff",x"c8",x"90",x"c1",x"91",x"2c"  ,x"0e",x"70",x"c8",x"99",x"86",x"01",x"b7",x"c8",
    x"56",x"ce",x"04",x"6a",x"ff",x"c8",x"90",x"b6"  ,x"c8",x"98",x"2a",x"45",x"f6",x"c8",x"96",x"b6",
    x"c8",x"a0",x"81",x"00",x"27",x"2b",x"c0",x"05"  ,x"c1",x"92",x"2c",x"4f",x"b6",x"c8",x"93",x"b1",
    x"c8",x"97",x"2c",x"0c",x"8b",x"14",x"b1",x"c8"  ,x"97",x"2d",x"11",x"70",x"c8",x"98",x"20",x"4b",
    x"80",x"05",x"b1",x"c8",x"97",x"2e",x"05",x"70"  ,x"c8",x"98",x"20",x"3f",x"86",x"00",x"b7",x"c8",
    x"a0",x"c1",x"80",x"2e",x"07",x"b7",x"c8",x"9e"  ,x"bd",x"03",x"44",x"39",x"5d",x"2b",x"1c",x"20",
    x"f4",x"f6",x"c8",x"96",x"c1",x"6a",x"2f",x"13"  ,x"86",x"6a",x"b7",x"c8",x"96",x"70",x"c8",x"98",
    x"86",x"01",x"b7",x"c8",x"56",x"ce",x"04",x"6a"  ,x"ff",x"c8",x"90",x"bd",x"f3",x"54",x"fc",x"c8",
    x"96",x"bd",x"f2",x"fc",x"8e",x"04",x"59",x"bd"  ,x"f3",x"ce",x"39",x"f6",x"c8",x"97",x"cb",x"02",
    x"b6",x"c8",x"93",x"8b",x"0a",x"b7",x"c8",x"ac"  ,x"f0",x"c8",x"ac",x"57",x"57",x"b6",x"c8",x"a6",
    x"3d",x"fb",x"c8",x"99",x"f7",x"c8",x"99",x"86"  ,x"01",x"8e",x"c9",x"1a",x"bd",x"f8",x"5e",x"86",
    x"01",x"8e",x"c9",x"2a",x"bd",x"f8",x"5e",x"7c"  ,x"c8",x"9f",x"7c",x"c8",x"a5",x"b6",x"c8",x"a5",
    x"81",x"05",x"26",x"16",x"7c",x"c8",x"a6",x"4f"  ,x"b7",x"c8",x"a5",x"7c",x"c8",x"98",x"b6",x"c8",
    x"98",x"81",x"0a",x"2f",x"05",x"86",x"0a",x"b7"  ,x"c8",x"98",x"b6",x"c8",x"99",x"81",x"00",x"26",
    x"1a",x"bd",x"f5",x"17",x"1f",x"89",x"c4",x"01"  ,x"c1",x"00",x"27",x"0f",x"4d",x"2a",x"07",x"86",
    x"ff",x"b7",x"c8",x"99",x"20",x"05",x"86",x"01"  ,x"b7",x"c8",x"99",x"b6",x"c8",x"98",x"b1",x"c8",
    x"a1",x"2d",x"0b",x"7c",x"c8",x"95",x"b6",x"c8"  ,x"a1",x"8b",x"02",x"b7",x"c8",x"a1",x"86",x"01",
    x"b7",x"c8",x"56",x"ce",x"04",x"62",x"ff",x"c8"  ,x"90",x"7e",x"02",x"6b",x"86",x"01",x"b7",x"c8",
    x"9e",x"b7",x"c8",x"a0",x"4f",x"b7",x"c8",x"97"  ,x"86",x"6a",x"b7",x"c8",x"96",x"86",x"ff",x"b7",
    x"c8",x"98",x"86",x"00",x"b7",x"c8",x"9a",x"b7"  ,x"c8",x"9c",x"bd",x"f5",x"17",x"84",x"03",x"1f",
    x"89",x"bd",x"f5",x"17",x"4d",x"2a",x"01",x"50"  ,x"f7",x"c8",x"99",x"86",x"00",x"b7",x"c8",x"9b",
    x"b7",x"c8",x"9d",x"39",x"86",x"01",x"b7",x"c8"  ,x"56",x"ce",x"04",x"72",x"ff",x"c8",x"90",x"b6",
    x"c9",x"49",x"b7",x"c9",x"49",x"bd",x"04",x"38"  ,x"bd",x"f1",x"92",x"bd",x"f2",x"89",x"bd",x"01",
    x"72",x"bd",x"01",x"2a",x"bd",x"04",x"2b",x"b6"  ,x"c8",x"a2",x"80",x"03",x"b7",x"c8",x"a2",x"b6",
    x"c9",x"3f",x"80",x"03",x"b7",x"c9",x"3f",x"b6"  ,x"c8",x"a4",x"80",x"03",x"b7",x"c8",x"a4",x"b6",
    x"c8",x"a3",x"80",x"03",x"b7",x"c8",x"a3",x"b6"  ,x"c9",x"49",x"80",x"06",x"24",x"c4",x"7a",x"c9",
    x"3b",x"bd",x"03",x"be",x"39",x"bd",x"f1",x"8b"  ,x"ce",x"04",x"7e",x"8e",x"c9",x"10",x"86",x"40",
    x"bd",x"f6",x"83",x"86",x"00",x"b7",x"c8",x"9e"  ,x"86",x"01",x"b7",x"c8",x"9f",x"8e",x"c9",x"1a",
    x"bd",x"f8",x"4f",x"86",x"35",x"b7",x"c9",x"3b"  ,x"cc",x"92",x"f6",x"fd",x"c8",x"92",x"8e",x"c9",
    x"2a",x"bd",x"f8",x"4f",x"4f",x"86",x"02",x"b7"  ,x"c8",x"95",x"86",x"02",x"b7",x"c8",x"94",x"86",
    x"03",x"b7",x"c8",x"a1",x"86",x"ff",x"b7",x"c9"  ,x"49",x"86",x"7f",x"b7",x"c8",x"a2",x"86",x"7f",
    x"b7",x"c9",x"3f",x"86",x"7f",x"b7",x"c8",x"a3"  ,x"86",x"7f",x"b7",x"c8",x"a4",x"4f",x"b7",x"c8",
    x"a5",x"4c",x"b7",x"c8",x"a6",x"39",x"bd",x"f1"  ,x"ba",x"cc",x"f1",x"60",x"fd",x"c8",x"2a",x"bd",
    x"f2",x"a9",x"bd",x"f1",x"af",x"86",x"01",x"b7"  ,x"c8",x"56",x"ce",x"fd",x"d3",x"ff",x"c8",x"90",
    x"bd",x"04",x"38",x"bd",x"f1",x"92",x"bd",x"f2"  ,x"89",x"ce",x"04",x"42",x"86",x"08",x"c6",x"a8",
    x"bd",x"f3",x"7a",x"bd",x"f1",x"ba",x"81",x"00"  ,x"27",x"e6",x"39",x"bd",x"f2",x"a9",x"bd",x"f3",
    x"54",x"ce",x"c9",x"10",x"bd",x"f3",x"85",x"39"  ,x"bd",x"f1",x"af",x"fe",x"c8",x"90",x"bd",x"f6",
    x"87",x"39",x"56",x"45",x"43",x"54",x"52",x"45"  ,x"58",x"20",x"50",x"4f",x"4e",x"47",x"80",x"47",
    x"41",x"4d",x"45",x"20",x"4f",x"56",x"45",x"52"  ,x"80",x"03",x"00",x"05",x"05",x"00",x"00",x"fb",
    x"fb",x"00",x"fd",x"69",x"fd",x"79",x"20",x"0a"  ,x"00",x"80",x"fd",x"69",x"fd",x"79",x"0a",x"0a",
    x"00",x"80",x"fe",x"66",x"fe",x"b6",x"07",x"12"  ,x"07",x"06",x"00",x"3c",x"18",x"80",x"fb",x"30",
    x"77",x"88",x"53",x"43",x"4f",x"52",x"45",x"3a"  ,x"30",x"30",x"30",x"30",x"30",x"30",x"80",x"fb",
    x"30",x"77",x"e2",x"48",x"49",x"54",x"53",x"3a"  ,x"30",x"30",x"30",x"30",x"30",x"30",x"80",x"fb",
    x"30",x"77",x"43",x"42",x"41",x"4c",x"4c",x"53"  ,x"3a",x"35",x"80",x"00",x"03",x"7f",x"00",x"14",
    x"05",x"00",x"00",x"ec",x"fb",x"00",x"02",x"7f"  ,x"70",x"00",x"00",x"70",x"90",x"00");


  
BEGIN

  ---------------------------------------------------------------
  Trace:PROCESS IS
    VARIABLE rad,wad : uv32;
    VARIABLE rcpt,rlen,wcpt,wlen : uint8;
    VARIABLE rdata,wdata : arr_uv32(0 TO 15);
    VARIABLE rpend,wpend : boolean;
    VARIABLE lout : Line;
  BEGIN
    wure(clksys);
    IF avl_read='1' AND avl_waitrequest='0' THEN
      rad:="00" & unsigned(avl_address);
      rpend:=true;
      rcpt:=0;
      rlen:=to_integer(unsigned(avl_burstcount));
    END IF;
    IF rpend AND avl_readdatavalid='1' THEN
      rdata(rcpt):=unsigned(avl_readdata);
      rcpt:=rcpt+1;
      IF rcpt=rlen THEN
        rpend:=false;
        write(lout,string'("R : " & to_hstring(rad) & ": "));
        FOR i IN 0 TO rlen-1 LOOP
          write(lout,to_hstring(rdata(i)) & " ");
        END LOOP;
        writeline(fil,lout);
      END IF;
    END IF;
    IF avl_write='1' AND avl_waitrequest='0' THEN
      IF NOT wpend THEN
        wad:="00" & unsigned(avl_address);
        wpend:=true;
        wcpt:=1;
        wlen:=to_integer(unsigned(avl_burstcount));
        wdata(0):=unsigned(avl_writedata);
      ELSE
        wdata(wcpt):=unsigned(avl_writedata);
        wcpt:=wcpt+1;
        IF wcpt=wlen THEN
          write(lout,string'("W : " & to_hstring(wad) & ": "));
          FOR i IN 0 TO rlen-1 LOOP
            write(lout,to_hstring(wdata(i)) & " ");
          END LOOP;
          writeline(fil,lout);
          wpend:=false;
        END IF;
      END IF;
    END IF;

    IF spot_en='1' THEN
      write(lout,"SPOT (" & to_hstring(spot_x) & "," &
            to_hstring(spot_y) & ") " & to_hstring(spot_z) & " >" &
            to_hstring("000" & spot_y(15 DOWNTO 6) & spot_x(15 DOWNTO 6) & '0')
            & "   [" & integer'image(to_integer(spot_x(15 DOWNTO 6)))
            & "," &  integer'image(to_integer(spot_y(15 DOWNTO 6)))
            & "]   " & time'image(now)
            );
      writeline(fil,lout);
    END IF;
    
  END PROCESS Trace;

  status<=x"0000_0000"; --40";
  
  ---------------------------------------------------------------
  i_vec_core: vec_core
    PORT MAP (
      sound             => sound,
      left_udlr         => left_udlr,
      left_x            => left_x,
      left_y            => left_y,
      right_udlr        => right_udlr,
      right_x           => right_x,
      right_y           => right_y,

      vga_r             => vga_r,
      vga_g             => vga_g,
      vga_b             => vga_b,
      vga_de            => vga_de,
      vga_hsyn          => vga_hsyn,
      vga_vsyn          => vga_vsyn,
      vga_hpos          => vga_hpos,
      vga_vpos          => vga_vpos,
      vga_clk           => vga_clk,
      vga_en            => vga_en,

      spot_x            => spot_x,
      spot_y            => spot_y,
      spot_z            => spot_z,
      spot_en           => spot_en,

      status            => status,
      pause             => pause,
      
      avl_clk           => avl_clk,
      avl_waitrequest   => avl_waitrequest,
      avl_readdata      => avl_readdata,
      avl_readdatavalid => avl_readdatavalid,
      avl_burstcount    => avl_burstcount,
      avl_writedata     => avl_writedata,
      avl_address       => avl_address,
      avl_write         => avl_write,
      avl_read          => avl_read,
      avl_byteenable    => avl_byteenable,

      vid_clk           => vid_clk,
      vid_waitrequest   => vid_waitrequest,
      vid_readdata      => vid_readdata,
      vid_readdatavalid => vid_readdatavalid,
      vid_burstcount    => vid_burstcount,
      vid_writedata     => vid_writedata,
      vid_address       => vid_address,
      vid_write         => vid_write,
      vid_read          => vid_read,
      vid_byteenable    => vid_byteenable,

      rom_clk           => rom_clk,
      rom_waitrequest   => rom_waitrequest,
      rom_readdata      => rom_readdata,
      rom_readdatavalid => rom_readdatavalid,
      rom_burstcount    => rom_burstcount,
      rom_writedata     => rom_writedata,
      rom_address       => rom_address,
      rom_write         => rom_write,
      rom_read          => rom_read,
      rom_byteenable    => rom_byteenable,

      host_download     => host_download,
      host_wr           => host_wr,
      host_addr         => host_addr,
      host_data         => host_data,
      host_wait         => host_wait,
      clksys            => clksys,
      reset_na          => reset_na);
  
  reset_na<='0','1' AFTER 4 us;
  clksys<=NOT clksys AFTER 1 us / 2 / 75;

  vga_clk<=clksys;
  
  --------------------------------------
  Avale:PROCESS IS
    VARIABLE a : unsigned(19 DOWNTO 0);
  BEGIN
    avl_readdatavalid<='0';
    wure(clksys);
    IF avl_write='1' AND avl_waitrequest='0' THEN
      a:=unsigned(avl_address(19 DOWNTO 0));
      FOR i IN 0 TO 6 LOOP
        mem(to_integer(a)+i):=unsigned(avl_writedata);
        wure(clksys);
        WHILE avl_waitrequest='1' LOOP
          wure(clksys);
        END LOOP;
      END LOOP;
      
    ELSIF avl_read='1' AND avl_waitrequest='0' THEN
      a:=unsigned(avl_address(19 DOWNTO 0));
--      wure(clksys);
      FOR i IN 0 TO 7 LOOP
        avl_readdata<=std_logic_vector(mem(to_integer(a)+i));
        avl_readdatavalid<='1';
        wure(clksys);
      END LOOP;
    END IF;
  END PROCESS Avale;

  PROCESS IS
  BEGIN
    wure(clksys);
    avl_waitrequest<='1';
    wure(clksys,5);
    avl_waitrequest<='0';
    wure(clksys,2);
    avl_waitrequest<='1';
    wure(clksys,3);
    avl_waitrequest<='0';
  END PROCESS;
  
  
  --------------------------------------
  Avale2:PROCESS IS
    VARIABLE a : unsigned(19 DOWNTO 0);
    VARIABLE f : natural;
    VARIABLE g : unsigned(15 DOWNTO 0);
  BEGIN
    vid_readdatavalid<='0';
    wure(clksys);
    IF vid_write='1' AND vid_waitrequest='0' THEN
      a:=unsigned(vid_address(19 DOWNTO 0));
      FOR i IN 0 TO 7 LOOP
        mem(to_integer(a)+i):=unsigned(vid_writedata);
        wure(clksys);
      END LOOP;
      
    ELSIF vid_read='1' AND vid_waitrequest='0' THEN
      a:=unsigned(vid_address(19 DOWNTO 0));
      wure(clksys);
      FOR i IN 0 TO 7 LOOP

        f :=to_integer(a(15 DOWNTO 0))+i;
        g :=to_unsigned(f,16);
        vid_readdata<=x"00" & std_logic_vector(g(15 DOWNTO 8)) &
                      x"00" & std_logic_vector(g(7 DOWNTO 0));
        --vid_readdata<=std_logic_vector(mem(to_integer(a)+i));
        vid_readdatavalid<='1';
        wure(clksys);
      END LOOP;
    END IF;
  END PROCESS Avale2;
  
  PROCESS IS
  BEGIN
    wure(clksys);
    vid_waitrequest<='0';
    wure(clksys,50);
    vid_waitrequest<='0';
    wure(clksys,2);
    vid_waitrequest<='0';
    wure(clksys,1);
    vid_waitrequest<='0';
  END PROCESS;



  -- ROM : 67 20 47 43 45 20 31 39
    --------------------------------------
  
  Avale3:PROCESS IS
    VARIABLE a : unsigned(19 DOWNTO 0);
  BEGIN
    rom_readdatavalid<='0';
    wure(clksys);
    IF rom_write='1' AND rom_waitrequest='0' THEN
      a:=unsigned(rom_address(19 DOWNTO 0));
      rom(to_integer(a)):=unsigned(rom_writedata);
      wure(clksys);
      
    ELSIF rom_read='1' AND rom_waitrequest='0' THEN
      a:=unsigned(rom_address(19 DOWNTO 0));
      wure(clksys);
      rom_readdata<=std_logic_vector(rom(to_integer(a)));
      rom_readdatavalid<='1';
      wure(clksys);

    END IF;
  END PROCESS Avale3;

  rom_waitrequest<='0';
  
  ROMInit:PROCESS IS
  BEGIN
    rom(0):=x"67204743";
    rom(1):=x"45203139";
    wait;
  END PROCESS ROMInit;

  UDLR:PROCESS IS
  BEGIN
    WAIT FOR 50 ms;
    left_udlr<="0011";
    right_udlr<="0011";
    WAIT FOR 50 ms;
    left_udlr<="0000";
    right_udlr<="0000";
    WAIT;
  END PROCESS UDLR;

  PROCESS IS
  BEGIN
    host_download<='0';
    host_wr<='0';

    WAIT FOR 5 us;
    host_download<='1';

    FOR i IN 0 TO cart'length/2-1 LOOP
      WAIT FOR 1 us;
      host_addr<=std_logic_vector('0' & to_unsigned(i*2,24));
      host_data<=std_logic_vector(cart(i*2+1)) & std_logic_vector(cart(i*2));
      host_wr<='1';
      WAIT FOR 1 us;
      host_wr<='0';
      
    END LOOP;
    host_download<='0';
    
    WAIT;
    

  END PROCESS;
  
    --host_download     : IN  std_logic;
    --  host_wr           : IN  std_logic;
    --  host_addr         : IN  std_logic_vector(24 DOWNTO 0);
    --  host_data         : IN  std_logic_vector(15 DOWNTO 0);
    --  host_wait         : OUT std_logic;
END ARCHITECTURE sim;

