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Category Archives: ARCH
MCU : TableWalking
If no internal TLB matches the current access, the MMU needs to find elsewhere the mapping information.
MCU : MMU TLBs and Pages
The MMU slices memory in pages.
MCU : Introducing the MMU
Now it’s time to describe the memory management unit and cache, glued together in the “MCU”.
Let’s begin with the MMU.
IU : Integer multiplication and division
First, there are two kinds of multipliers and dividers in our CPU, the integer and the floating point ones. They are a bit different.
IU : Condition codes
SPARC CPUs use condition codes, the famous NZVC bits (Negative, Zero, ‘Verflow and Carry).
IU : Pipelined : Multicycle
Some instructions last more than one cycle, even on RISC CPUs.
IU : Pipelined : Stall and Bypass
Integer registers are read at the beginning of the EXECUTE stage and are updated at the end of the WRITE stage.
IU : Pipelined : Traps
There are many circumstances where a CPU may halt and jump to an exception vector:
IU : Pipelined : PIPE5 presentation
This is the traditional RISC implementation, the one you find in hundreds of CPU cores, thousands of books, millions of computer architecture courses, gazillions chips.