The next article is the first in a series about CPU architecture and design.
These articles will try to describe how the [simple, primitive] cores in TEMLIB actually work, they won’t explain the latest technological advances and architectural refinements found in current billion transistors processors (affordable FPGAs are too small anyway…).
Basic knowledge of digital design is expected.
Knowing VHDL and having read the SparcV8 standard can help as well.
I will try to mix general topics with details that struck me while trying to make stuff work. I will also try to compare some SPARC design choices with obscure competitors like x86, ARM, PowerPC, MIPS… Most of the things covered in these articles will be already present in the TEMLIB cores. Nevertheless some details or alternatives that will be exposed for completeness may be unavailable.
CPU architecture covers many widely different subjects: pipeline design, floating point math, memory and cache operation… Many articles will be needed to cover all these aspects as several options will be explored in TEMLIB: Different architectures, cache mechanisms, dividers implementations, etc.
There is a lot to learn as well from small details and tricky aspects: A scalar pipeline is simple to understand, the hard part is the relations with the FPU, handling traps, etc.
“Real” CPU architects could probably find tons of errors and argue about all sorts of alternative solutions. Every effort will be made to ignore them. Being exhaustive is not the goal.
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Here we go….