CPU structure

CPUs are made of several subparts.

We use the decomposition below.


IU: Integer Unit

The essential part of the CPU: Executes almost all instructions, manages memory accesses for data and instruction fetches and includes integer registers and supervisor control registers. The IU includes the following sub-blocs:

    • ALU: Arithmetic and Logic Unit: For add, sub, and, or, not, compare…
    • MDU: Integer Multiply and Divide Unit
    • LSU: Load Store Unit

(The Unit term is a bit too generous!)

FPU: Floating Point Unit

Our floating point unit is a separate block that is provided with instructions by the IU and performs calculations on a dedicated set of registers. The FPU is somewhat independent and can execute long latency instructions (for example a division) without stalling the integer part.

MCU: Memory and Cache Unit

This part does both Memory Management (virtual memory, protection mechanisms,…) and caching. For our CPU, cache lookup and address translations are done simultaneously and are closely tied together.

The MCU and FPU parts are optional, some very serviceable CPUs have neither.

In TEMLIB, three compatible IUs are currently available: IU_SIM, IU_SEQ and IU_PIPE5. There is currently only one MCU (uniprocessor, write through) and one FPU (non pipelined, slow and not even small)

Remember these acronyms, you will see them often.

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