IU : Simulation

Writing VHDL code can be very much like software programming.

The sequential part of VHDL is very similar to ADA and concurrency is also, for better or worse, widely present in software.

TEMLIB features several compatible CPU implementations which share some building blocks: IU_SEQ, IU_PIPE5 and IU_SIM [and <censored>]

Using functions and procedures to implement combinatorial functions (instead of entities), it is possible to build a simulation-only CPU which use no internal signal, whose all registers are variables. This CPU works a bit like a software emulator written in C.

As it avoids signals, IU_SIM simulation speed is tolerable. It doesn’t have the same clock for clock execution speed as either IU_SEQ or IU_PIPE5 though.

The FPU is perfect and can execute everything in one cycle (even a division) using simple behavioural descriptions. It was used as a reference for the real FPU, which must pipeline calculations and reuse hardware.


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