TEMLIB r1

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The TEMLIB archive currently includes the following blocks:

 CPU

  • Several integer units: Simulation, Sequential, Pipelined
  • Basic FPU
  • Basic MMU and Cache controller (VIVT)

Glue

  • Internal busses management: PLOMB, PVC

Generic peripherals

  • Internal RAM (Xilinx BlockRAM and simulation models)
  • External asynchronous 32bits RAM and 16bits FLASH interfaces
  • Minimal serial asynchronous port
  • Video framebuffer

Workstation

  • The target is a Sun SparcStation 5 workstation.
  • Currently available

-RAM

-Interrupt controller

-IOMMU

-FLASH (for the OpenBIOS firmware)

-Hard disk (using a CompactFLASH memory card)

-Ethernet 10/100Mbps

-Serial Ports

  • Limitations

-Crappy disk performance

-No video, mouse, keyboard

-No sound

-No floppy

-No CDROM

-No time keeping real time clock.

Target boards

  • Altium LiveDesign Evaluation board.

Spartan3S400.

Simple design with CPU, cache, video, RAM, serial port.

  • Xilinx SP605 board

Spartan6VLX45L

Workstation

Read the manual for details.

Some parts use Xilinx hard macros (block RAM, PLL, Spartan6 DRAM controller, SystemACE) but most of the code is target-agnostic.