PLOMB pipes

The “Altium LiveDesign evaluation kit” features 1MB fast asynchronous RAM memory in addition to the 16kB available inside the FPGA.


In the altium.vhd design, there is a CPU and a video framebuffer controller which can both initiate memory accesses.

The cores use the PLOMB interconnect. PLOMB links are point to point and can be combined with MUX and SEL blocks for building any topology. The PVC bus is a simpler variant.

Both are described in the manual.

One bus


In this configuration, all accessses pass through a single PLOMB link. On the MUX block, port 0 has highest priority, it should be given to VID to ensure a stable image.

The VID bus is read-only: VID reads pixels from memory.

Separate busses


This configuration allows simultaneous accesses by the CPU to the internal RAM and registers and the video controller to the external RAM. Performance is better, particularly when the program is executed from the internal RAM.



Here is the complete configuration with crossbar connections allowing simultaneous accesses and flexible storage of code and data in external and internal RAM.

Cache controller


This configuration is the most complex, with a cache for the CPU enabling simultaneous accesses for data, instructions and video.

The cache controller is write-through, the displayed area can be cache-enabled.

Any topology can be built with PLOMB …

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