Something

Hello all.

It’s been a long, long time since that blog was last updated.

I’ve been using temlib.org to host some files, such as things in temlib.org/pub, or as a temporary home for the Atari-Forum Wiki. And having own email addresses can be quite useful. So I’m not about to ditch that site. WordPress should probably be replaced with some static site generator though.

What has changed?

– I have made a few contributions to the MiSTer project, such as the ASCAL open-source scaler, a Mattel Intellivision core, or an upcoming Fairchild Channel F core, and a few other things. The scaler would definitely deserve a post about how it works, design tradeoffs.

– For the SparcStation, many things have changed since the last published version, I’ll release the new sources eventually. Current development platform is MiSTer which has a larger FPGA than the old Xilinx SP605.

The biggest thing which was missing in the SparcStation was the support of SMP = Multiprocessing = SparcStation 10/20. With latest changes, I have managed to run the old RedHat with 3 CPUs on the large MiSTer FPGA. Uses a coherent MESI cache architecture. Other OS may be supported, maybe.

The problem with implementing old stuff, is that being compliant with the spec. isn’t just enough. The old Red Hat Linux triggers TLB flushes through IPC as there is no inter-CPU TLB invalidation mechanism. It is possible to do full TLB invalidation, it is also possible to invalidate only select TLB entries. In uniprocessor mode full TLB flushes work, but are a bit inefficient. In SMP mode, some race condition somewhere makes full invalidation go wrong.

There are actually quite a bit of weird details and bugs in 32bits SPARC CPUs which had to be replicated, something that I didn’t anticipate when I chose the SparcStation as a “computer in a FPGA” project. I chose it because it was well documented, with no issue on licensing the SPARC architecture, and supported many different OSes.

(Of course, now there are gazillions RISC-V projects, but it’s too simple. And, does RISC-V support genuine NextSTEP or SunOS? 😉

I still have many projects, not enough time and many difficult times where it is hard to motivate oneself on weird stuff like FPGAs. Latest developments around MiSTer and FPGAs for gaming makes it more motivating as people are now far more interested than 5 years ago.

So, I need to check latest version with SMP and faster CPU with different OSes, and makes versions for MiSTer, Xilinx SP605 and Terasic C5G.

2 thoughts on “Something

  1. These are amazing news. Your contibutions in MiSTer are priceless and experiencing your SparcStation core so to run SunOS and NextSTEP/OpenStep… well, what can I say? It’s just anotherdream made true !

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