Something

Hello all.

It’s been a long, long time since that blog was last updated.

I’ve been using temlib.org to host some files, such as things in temlib.org/pub, or as a temporary home for the Atari-Forum Wiki. And having own email addresses can be quite useful. So I’m not about to ditch that site. WordPress should probably be replaced with some static site generator though.

What has changed?

– I have made a few contributions to the MiSTer project, such as the ASCAL open-source scaler, a Mattel Intellivision core, or an upcoming Fairchild Channel F core, and a few other things. The scaler would definitely deserve a post about how it works, design tradeoffs.

– For the SparcStation, many things have changed since the last published version, I’ll release the new sources eventually. Current development platform is MiSTer which has a larger FPGA than the old Xilinx SP605.

The biggest thing which was missing in the SparcStation was the support of SMP = Multiprocessing = SparcStation 10/20. With latest changes, I have managed to run the old RedHat with 3 CPUs on the large MiSTer FPGA. Uses a coherent MESI cache architecture. Other OS may be supported, maybe.

The problem with implementing old stuff, is that being compliant with the spec. isn’t just enough. The old Red Hat Linux triggers TLB flushes through IPC as there is no inter-CPU TLB invalidation mechanism. It is possible to do full TLB invalidation, it is also possible to invalidate only select TLB entries. In uniprocessor mode full TLB flushes work, but are a bit inefficient. In SMP mode, some race condition somewhere makes full invalidation go wrong.

There are actually quite a bit of weird details and bugs in 32bits SPARC CPUs which had to be replicated, something that I didn’t anticipate when I chose the SparcStation as a “computer in a FPGA” project. I chose it because it was well documented, with no issue on licensing the SPARC architecture, and supported many different OSes.

(Of course, now there are gazillions RISC-V projects, but it’s too simple. And, does RISC-V support genuine NextSTEP or SunOS? 😉

I still have many projects, not enough time and many difficult times where it is hard to motivate oneself on weird stuff like FPGAs. Latest developments around MiSTer and FPGAs for gaming makes it more motivating as people are now far more interested than 5 years ago.

So, I need to check latest version with SMP and faster CPU with different OSes, and makes versions for MiSTer, Xilinx SP605 and Terasic C5G.

10 thoughts on “Something

  1. These are amazing news. Your contibutions in MiSTer are priceless and experiencing your SparcStation core so to run SunOS and NextSTEP/OpenStep… well, what can I say? It’s just anotherdream made true !

      • Its good to hear an update from you!

        Great updates, also if you check the port-sparc mailing list at netbsd, you’ll find there is quite an interesting discussion going on with building a new sbus card around fast FPGA, and potentially being able to snoop sbus which might be useful for reverse engineering.

        Sadly mainline Linux is dropping sun4m/d support the patches were just posted, probably not a big deal though. NetBSD is a much better OS to work with on such old machines anyway… .I do wish the package management was more like gentoo or Archlinux though, I guess pkgin kind of fills that need.

        Do you think it would be possible to fit, 2 CPUs + full CG14/SX emulation in? That would allow graphics to be sped up a bit with the NetBSD drivers.

        -chase

        • Thank you Chase! The SparcStation core is progressing, but often slowly.
          Managing to boot good old RedHat in SMP mode was quite a challenge. Is current Sparc32 NetBSD SMP mode working now?

          I once asked a while ago on the Linux-kernel ML to delay dropping Sun4m, but now I think it’s done, as distros don’t support it anymore. They keep LEON which is a bit different from the various SPARC CPUs that Sun used. LEON CPUs are used in embedded designs (satellites…), and run real-time OSes such as RTEMS, I have some doubts that Linux support is really useful anyway.

          The CG14 uses DRAM directly as video framebuffer, this is the same as the FPGA which used the same RAM for the OS and as a framebuffer, so performance is quite better than through SBUS. There is very basic acceleration in the TCX mode, used by NetBSD and NextSTEP.

          MiSTer FPGA (DE10nano) can fit 3 CPUs, the FPGA on the C5G at least 2. Maybe 4 CPUs could fit on the MiSTer but then it would severely reduce working frequency.

          • I think they got the SMP bugs out of Netbsd.. it was having there for a bit. I haven’t tested but I may play around with it over christmas.

          • Hello,

            Been running NetBSD 9.0 on SPARCstation 20s, SMP works fine – I’ve tested SM61 (60 MHZ SuperSPARC I), but also mixed-frequency HyperSPARC and even quad-CY7C601 (dual SM100) without an issue. I recommend it as the modern OS of choice.

    • I didn’t try the 64bits open Sparc core. Likely needs pretty large FPGA.
      Cheap FPGAs such as Cyclone V can run 32bits SPARCs with frequency comparable to actual 90’s chips. And with no special video acceleration. So software from that time is useable.

      Even if I could fit an UltraSparc CPU in the FPGA, it would run at less than 50MHz, and software, operating systems would be likely unbearably slow (except for simple OSes such as NetBSD, I suppose)

  2. I recently came accross your SparcStation core (on MiSTerFPGA) and I was BLOWN AWAY ! It is amazing ! I would love having a more stable NeXTStep experience, but it already incredible. I think it deserves way more recognition.

    I have a 1.5m wall of SparcStations (1,5,10 & 20) : https://kuk.re/9d6f77

    If I can be of any help please ask. I am mostly an old-school sysadmin + script/perl/python/c coder but you never know !

    Thanks so much for your work !

    • Thank you very much.
      That’s an impressive stack. I only have 6 SparcStations : 2 SS5, 1 SS10, 1 SS20 (2 CPUs), 1 Ultra10 and 1 Blade1000 (2 CPUs)

      There are some strong evidence than NeXTStep for Sparc wasn’t very polished and that there are some bugs (for example it does erroneous memory allocation requests to the BIOS during boot).
      I wish more interesting software could be available for NeXTStep, Solaris.

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