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8bits I/F
MEM
DRAM
IO
IOMMU
PLOMB_MIG
TS_IOMMU
TS_IO
TS_CORE
MIG interface
SCSI-like
Ethernet MAC I/F
TS_ESP
TS_LANCE
XilinxSystemACE
Ethernet MII
DDR3DRAM
TS_RTC
TS_SPORT
TS_SPORT
NVRAM
ACIA
ACIA
AFLASH
ParallelNOR FLASH
BRAM(boot loader)
TS_TIMER
TS_INTER
TS_DECODE
PVC
Multiplexerread back
Addressdecoderselections
IRL
(interrupt ctrl.)
Interruptsources
int.
int.
int.
int.
int.
Async.serial
(2 serial ports)
(SCSI ctrl.)
(Ethernet ctrl.)
(DMA remapping)
ACIA
ACIA
SCSI_SYSACE
TS_LANCE_MAC
MIG(XilinxCoreGen)
USB-RS232interface
EXT
INST
DATA
IRL
RESET
FPU_REGS
FPU
IU
IU_REGS
MCU
D-cache
I-cache
CPUCORE
RESET
SP605_TS (FPGA top)
SEL
PLOMB
MUX
PLOMB
PLOMB
MUX
PLOMB
PLOMB_R
PLOMB_W
PLOMB_R
PLOMB_W
PVC bus
PLOMB bus
ClockPLLs(Xilinx)
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