https://www.temlib.org/AtariForumWiki/api.php?action=feedcontributions&feedformat=atom&user=Cyprian 2026-05-02T12:10:30Z User contributions MediaWiki 1.39.2 https://www.temlib.org/AtariForumWiki/index.php?title=Atari_ST/STe/MSTe/TT/F030_Hardware_Register_Listing&diff=22858 2024-01-27T01:40:43Z

<p>Cyprian: A new label for $FF82C2 - Video Mode (VDM)</p> <hr /> <div>Based on:<br /> * https://temlib.org/AtariForumWiki/index.php/Atari_ST/STe/MSTe/TT/F030_Hardware_Register_Listing<br /> * https://github.com/Number0000009/atari-wiki/blob/master/Atari%20ST%20STe%20MSTe%20TT%20F030%20Hardware%20Register%20Listing.txt<br /> * https://mikro.naprvyraz.sk/docs/Memory%20Maps/FALREG.TXT<br /> * https://mikro.naprvyraz.sk/docs/mikro/videl.html<br /> * http://cd.textfiles.com/atarilibrary/atari_cd10/DISKS/AC10DISK/ATOZBOOK/M.TXT<br /> <br /> &lt;pre&gt;<br /> .---------------------------------------------------.<br /> |Atari ST/STe/MSTe/TT/F030 Hardware Register Listing|<br /> `---------------------------------------------------'<br /> <br /> <br /> <br /> Address Description Space<br /> -------+----------------------------------------------------------------+-----<br /> ########CPU Reset Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $000000|Reset : Initial SSP |SP<br /> $000004|Reset : Initial PC |SP<br /> -------+----------------------------------------------------------------+-----<br /> ########CPU Exception Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $000008|Bus Error |SD<br /> $00000C|Address Error |SD<br /> $000010|Illegal Instruction |SD<br /> $000014|Zero Divide |SD<br /> $000018|CHK, CHK2 Instruction |SD<br /> $00001C|cpTRAPcc, TRAPcc, TRAPV |SD<br /> $000020|Privilege Violation |SD<br /> $000024|Trace |SD<br /> $000028|Line 1010 Emulator (LineA) |SD<br /> $00002C|Line 1111 Emulator (LineF) |SD<br /> $000030|(Unassigned, Reserved) |SD<br /> $000034|Coprocessor Protocol Violation (68030) |SD<br /> $000038|Format Error (68010) |SD<br /> $00003C|Uninitialized Interrupt Vector |SD<br /> $000040|(Unassigned, Reserved) |SD<br /> : | : : | :<br /> $00005F|(Unassigned, Reserved) |SD<br /> $000060|Spurious Interrupt (Bus error during interrupt) |SD <br /> -------+----------------------------------------------------------------+-----<br /> ########Auto-Vector Interrupts ######<br /> -------+----------------------------------------------------------------+-----<br /> $000064|Level 1 Int Autovector (TT VME) |SD<br /> $000068|Level 2 Int Autovector (HBL) |SD<br /> $00006C|Level 3 Int Autovector (TT VME) |SD<br /> $000070|Level 4 Int Autovector (VBL) |SD<br /> $000074|Level 5 Int Autovector |SD<br /> $000078|Level 6 Int Autovector (MFP) |SD<br /> $00007C|Level 7 Int Autovector |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########Trap Instruction Vectors (Trap #n = Vector number + 32 + n) ######<br /> -------+----------------------------------------------------------------+-----<br /> $000080|Trap #0 |SD<br /> $000084|Trap #1 (GemDOS) |SD<br /> $000088|Trap #2 (AES/VDI) |SD<br /> $00008C|Trap #3 |SD<br /> $000090|Trap #4 |SD<br /> $000094|Trap #5 |SD<br /> $000098|Trap #6 |SD<br /> $00009C|Trap #7 |SD<br /> $0000A0|Trap #8 |SD<br /> $0000A4|Trap #9 |SD<br /> $0000A8|Trap #10 |SD<br /> $0000AC|Trap #11 |SD<br /> $0000B0|Trap #12 |<br /> $0000B4|Trap #13 (BIOS) |SD<br /> $0000B8|Trap #14 (XBIOS) |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########Math Coprocessor Vectors (68881/68882/Internal) ######<br /> -------+----------------------------------------------------------------+-----<br /> $0000C0|FFCP Branch or Set on Unordered Condition |SD<br /> $0000C4|FFCP Inexact Result |SD<br /> $0000C8|FFCP Divide by Zero |SD<br /> $0000CC|FFCP Underflow |SD<br /> $0000D0|FFCP Operand Error |SD<br /> $0000D4|FFCP Overflow |SD<br /> $0000D8|FFCP Signaling NAN |SD<br /> $0000DC|(Unassigned, Reserved) |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########PMMU Coprocessor Vectors (68851/Internal) ######<br /> -------+----------------------------------------------------------------+-----<br /> $0000E0|MMU Configuration Error |SD<br /> $0000E4|MC68851, not used by MC68030 |SD<br /> $0000E8|MC68851, not used by MC68030 |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########Miscellaneous Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $0000EC|(Unassigned, Reserved) |SD<br /> : | : : | :<br /> $0000FF|(Unassigned, Reserved) |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########User Assigned Interrupt Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $000100|ST-MFP-0 - Centronics busy |SD<br /> $000104|ST-MFP-1 - RS-232 DCD |SD<br /> $000108|ST-MFP-2 - RS-232 CTS |SD<br /> $00010C|ST-MFP-3 - Blitter done |SD<br /> $000110|ST-MFP-4 - Timer D (USART timer) |SD<br /> $000114|ST-MFP-5 - Timer C (200hz Clock) |SD<br /> $000118|ST-MFP-6 - Keyboard/MIDI (ACIA) |SD<br /> $00011C|ST-MFP-7 - FDC/HDC |SD<br /> $000120|ST-MFP-8 - Timer B (HBL) |SD<br /> $000124|ST-MFP-9 - Send Error |SD<br /> $000128|ST-MFP-10 - Send buffer empty |SD<br /> $00012C|ST-MFP-11 - Receive error |SD<br /> $000130|ST-MFP-12 - Receive buffer full |SD<br /> $000134|ST-MFP-13 - Timer A (STe sound) |SD<br /> $000138|ST-MFP-14 - RS-232 Ring detect |SD<br /> $00013C|ST-MFP-15 - GPI7 - Monochrome Detect |SD<br /> $000140|TT-MFP-0 - GPI 0 |SD<br /> $000144|TT-MFP-1 - GPI 1 |SD<br /> $000148|TT-MFP-2 - SCC-DMA Controller |SD<br /> $00014C|TT-MFP-3 - Ring Indicator SCC B |SD<br /> $000150|TT-MFP-4 - Timer D |SD<br /> $000154|TT-MFP-5 - Timer C |SD<br /> $000158|TT-MFP-6 - (Reserved) GPI 4 |SD<br /> $00015C|TT-MFP-7 - SCSI DMA Controller |SD<br /> $000160|TT-MFP-8 - Timer B |SD<br /> $000164|TT-MFP-9 - Send Error |SD<br /> $000168|TT-MFP-10 - Send buffer empty |SD<br /> $00016C|TT-MFP-11 - Receive error |SD<br /> $000170|TT-MFP-12 - Receive buffer full |SD<br /> $000174|TT-MFP-13 - Timer A |SD<br /> $000176|TT-MFP-14 - TT Clock (MC146818A) |SD<br /> $00017C|TT-MFP-15 - TT-SCSI Drive Controller NCR 5380 |SD<br /> $000180|SCC Interrupt |SD<br /> $0001BC|SCC Interrupt |SD<br /> $0001C0|User Defined, Unused |SD<br /> : | : : : | :<br /> $0003FC|User Defined, Unused |SD<br /> -------+----------------------------------------------------------------+-----<br /> <br /> Address Size Description Name<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############System Crash Page ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $000380|long |Validates System Crash Page if $12345678 |proc_lives<br /> $000384|.....|Saved registers D0-D7 |proc_dregs<br /> $0003A4|.....|Saved registers A0-A7 |proc_aregs<br /> $0003C4|long |Vector number of crash exception |proc_enum<br /> $0003C8|long |Saved USP |proc_usp<br /> $0003CC|.....|Saved 16 words from exception stack |proc_stk<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############System Variables ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $000400|long |GEM Event timer vector |etv_timer<br /> $000404|long |GEM Critical error handler |etv_critic<br /> $000408|long |GEM Program termination vector |etv_term<br /> $00040C|long |GEM Additional vector #1 (Unused) |etv_xtra<br /> : | : | : : : : : | :<br /> $00041C|long |GEM Additional vector #5 (Unused) |etv_xtra<br /> $000420|long |Validates memory configuration if $752019F3 |memvalid<br /> $000424|word |Copy of contents of $FF8001 |memctrl<br /> $000426|long |Validates resvector if $31415926 |resvalid<br /> $00042A|long |Reset vector |resvector<br /> $00042E|long |Physical top of RAM |phystop<br /> $000432|long |Start of TPA (user memory) |_membot<br /> $000436|long |End of TPA (user memory) |_memtop<br /> $00043A|long |Validates memcntrl and memconf if $237698AA |memval2<br /> $00043E|word |If nonzero, floppy disk VBL routine is disabled |flock<br /> $000440|word |Floppy Seek rate - 0:6ms, 1:12ms, 2:2ms, 3:3ms |seekrate<br /> $000442|word |Time between two timer calls (in milliseconds) |_timer_ms<br /> $000444|word |If not zero, verify floppy disk writes |_fverify<br /> $000446|word |Default boot device |_bootdev<br /> $000448|word |0 - NTSC (60hz), &lt;&gt;0 - PAL (50hz) |palmode<br /> $00044A|word |Default video resolution |defshiftmod<br /> $00044C|word |Copy of contents of $FF8260 |sshiftmod<br /> $00044E|long |Pointer to video RAM (logical screen base) |_v_bas_ad<br /> $000452|word |If not zero, VBL routine is not executed |vblsem<br /> $000454|word |Number of vertical blank routines |nvbls<br /> $000456|long |Pointer to list of vertical blank routines |_vblqueue<br /> $00045A|long |If not zero, points to color palette to be loaded |colorptr<br /> $00045E|long |If not zero, points to video ram for next VBL |screenpt<br /> $000462|long |Counter for number of VBLs |_vbclock<br /> $000466|long |Number of VBL routines executed |_frclock<br /> $00046A|long |Vector for hard disk initialization |hdv_init<br /> $00046E|long |Vector for resolution change |swv_vec<br /> $000472|long |Vector for getbpb for hard disk |hdv_bpb<br /> $000476|long |Vector for read/write routine for hard disk |hdv_rw<br /> $00047A|long |Vector for hard disk boot |hdv_boot<br /> $00047E|long |Vector for hard disk media change |hdv_mediach<br /> $000482|word |If not zero, attempt to load &quot;COMMAND.PRG&quot; on boot |_comload<br /> $000484|byte |Attribute vector for console output BIT 3 2 1 0|conterm<br /> | |Return &quot;kbshift&quot; for BIOS conin --------------' | | ||<br /> | |System bell (1 - on) ---------------------------' | ||<br /> | |Key repeat (1 - on) ------------------------------' ||<br /> | |Key click (1 - on) ---------------------------------'|<br /> $000486|long |Return address for TRAP #14 (unused)|trp14ret<br /> $00048A|long |Return address for critical error handler (unused)|criticret<br /> $00048E|long |Memory descriptor block |themd<br /> $00049E|long |Space for additional memory descriptors |themdmd<br /> $0004A2|long |Pointer to BIOS save registers block |savptr<br /> $0004A6|word |Number of connected floppy drives |_nflops<br /> $0004A8|long |Vector for screen output |con_state<br /> $0004AC|word |Temporary storage for cursor line position |save_row<br /> $0004AE|long |Pointer to save area for exception processing |sav_context<br /> $0004B2|long |Pointer to buffer control block for GEMDOS data |_bufl<br /> $0004B6|long |Pointer to buffer control block for GEMDOS fat/dir |_bufl<br /> $0004BA|long |Counter for 200hz system clock |_hz_200<br /> $0004BC|long |Pointer to default environment string |the_env<br /> $0004C2|long |Bit allocation for physical drives (bit 0=A, 1=B..) |_drvbits<br /> $0004C6|long |Pointer to 1024-byte disk buffer |_dskbufp<br /> $0004CA|long |Pointer to autoexecute path |_autopath<br /> $0004CE|long |Pointer to VBL routine #1 |_vbl_lis<br /> : | : | : : : : : | :<br /> $0004EA|long |Pointer to VBL routine #8 |_vbl_lis<br /> $0004EE|word |Flag for screen -&gt; printer dump |_dumpflg<br /> $0004F0|word |Printer abort flag |_prtabt<br /> $0004F2|long |Pointer to start of OS |_sysbase<br /> $0004F6|long |Global shell pointer |_shell_p<br /> $0004FA|long |Pointer to end of OS |end_os<br /> $0004FE|long |Pointer to entry point of OS |exec_os<br /> $000502|long |Pointer to screen dump routine |scr_dump<br /> $000506|long |Pointer to _lstostat() |prv_lsto<br /> $00050A|long |Pointer to _lstout() |prv_lst<br /> $00050E|long |Pointer to _auxostat() |prv_auxo<br /> $000512|long |Pointer to _auxout() |prv_aux<br /> $000516|long |If AHDI, pointer to pun_info |pun_ptr<br /> $00051A|long |If $5555AAAA, reset |memval3<br /> $00051E|long |8 Pointers to input-status routines |xconstat<br /> $00053E|long |8 Pointers to input routines |xconin<br /> $00055E|long |8 Pointers to output-status routines |xcostat<br /> $00057E|long |8 Pointers to output routines |xconout<br /> $00059E|word |If not 0, then not 68000 - use long stack frames |_longframe<br /> $0005A0|long |Pointer to cookie jar |_p_cookies<br /> $0005A4|long |Pointer to end of FastRam |ramtop<br /> $0005A8|long |Validates ramtop if $1357BD13 |ramvalid<br /> $0005AC|long |Pointer to routine for system bell |bell_hook<br /> $0005B0|long |Pointer to routine for system keyclick |kcl_hook<br /> -------+-----+-----------------------------------------------------+----------<br /> <br /> Address Size Description Bits used Read/Write<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############OS ROMs ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $E00000|byte |TOS 512k ROMs |R<br /> : | : | : : : |:<br /> $EFFFFF|byte |TOS 512k ROMs |R<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############ADSPEED Configuration registers ########### <br /> -------+-----+-----------------------------------------------------+----------<br /> $F00000|byte |Switch to 16 Mhz |W<br /> $F10000|byte |Switch to 8 Mhz |W<br /> $F20000|byte |Turn on high speed ROM option in 16 Mhz |W<br /> $F30000|byte |Turn off high speed ROM option |W<br /> $F40000|byte |Unknown |W<br /> $F50000|byte |Turn off cache while in 16 Mhz |W<br /> | | &gt;&gt; Write 0 to an address to set it. &lt;&lt; |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############IDE Controller (Falcon, ST-Book, IDE cards) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $F00000|word |Data Register |R/W<br /> | | BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0|<br /> $F00002|word |Data Register |R/W<br /> | | BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0|<br /> $F00005|byte |Error Register BIT 7 6 5 4 3 2 1 0|R<br /> | |Bad block mark -----------------------' | | | | | | ||<br /> | |Uncorrectable error --------------------' | | | | | ||<br /> | |Media change -----------------------------' | | | | ||<br /> | |ID-Field not found -------------------------' | | | ||<br /> | |Media change requested -----------------------' | | ||<br /> | |Command aborted --------------------------------' | ||<br /> | |Track 0 not found --------------------------------' ||<br /> | |DAM not found --------------------------------------'|<br /> $F00005|byte |Write Precompensation |W<br /> $F00009|byte |Sector Count Register |W<br /> $F0000D|byte |Sector Number Register |W<br /> $F00011|byte |Cylinder Low Register BIT 7 6 5 4 3 2 1 0|W<br /> $F00015|byte |Cylinder High Register BIT 1 0|W<br /> $F00019|byte |Drive Head Register BIT 7 6 5 4 3 2 1 0|W<br /> | |Sector size (512 bytes, fixed) -------+ + + | | | | ||<br /> | |Drive (0 - Master, 1 - Slave) --------------' | | | ||<br /> | |Head number ----------------------------------+ + + +|<br /> $F0001D|byte |Status Register BIT 7 6 5 4 3 2 1 0|R<br /> | |Drive busy with executing Command ----' | | | | | | ||<br /> | |Drive Ready ----------------------------' | | | | | ||<br /> | |Drive Write Fault ------------------------' | | | | ||<br /> | |Drive Seek Complete ------------------------' | | | ||<br /> | |Data Request ---------------------------------' | | ||<br /> | |Corrected Data ---------------------------------' | ||<br /> | |Index pulse --------------------------------------' ||<br /> | |Error ----------------------------------------------'|<br /> $F0001D|byte |Command Register |W<br /> $F00039|byte |Alternate Status Register |R<br /> | |2nd status register, like 1st no deletion of the IRQ | |<br /> $F00039|byte |Data Output Register BIT 2 1 .|W<br /> | |Software Reset (1 - on)-------------------------+ | |<br /> | |Interrupt after end of Command (0 - on) ----------+ |<br /> $F0003D|byte |Active address BIT 6 5 4 3 2 1 0|R<br /> | |Drive is writing (0 - on) --------------' | | | | | ||<br /> | |Negated number of head number ------------+ + + + | ||<br /> | |Slave Drive Select (0 - on) ----------------------' ||<br /> | |Master Drive Select (0 - on) -----------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############OS ROMs ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FC0000|byte |TOS 192k ROMs |R<br /> : | : | : : : |:<br /> $FEFFFF|byte |TOS 192k ROMs |R<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############ST MMU Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8001|byte |MMU memory configuration BIT 3 2 1 0|R/W<br /> | |Bank 0 | | | ||<br /> | |00 - 128k ------------------------------------+-+ | ||<br /> | |01 - 512k ------------------------------------+-+ | ||<br /> | |10 - 2m --------------------------------------+-+ | ||<br /> | |11 - reserved --------------------------------+-' | ||<br /> | |Bank 1 | ||<br /> | |00 - 128k ----------------------------------------+-+|<br /> | |01 - 512k ----------------------------------------+-+|<br /> | |10 - 2m ------------------------------------------+-+|<br /> | |11 - reserved ------------------------------------+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon030 Processor Control ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8007|byte |Falcon Bus Control BIT 6 5 . 3 2 . 0|R/W (F030)<br /> | |RESET behavior -------------------------+ | | | ||<br /> | | 0 = always cold start ----------------+ | | | ||<br /> | | 1 = normal, &quot;memvalid&quot; is observed ---+ | | | ||<br /> | |STe Bus Emulation ------------------------' | | ||<br /> | | 0 = STE --------------------------------' | | ||<br /> | | 1 = Falcon -----------------------------' | | ||<br /> | |Blitter flag ---------------------------------' | ||<br /> | | 0 = BLiTTER On -----------------------------' | ||<br /> | | 1 = BLiTTER Off ----------------------------' | ||<br /> | |Blitter clock-----------------------------------' ||<br /> | | 0 - 8mhz, ------------------------------------' ||<br /> | | 1 - 16mhz ------------------------------------' ||<br /> | |68030 clock ----------------------------------------'|<br /> | | 0 - 8mhz -----------------------------------------'|<br /> | | 1 - 16mhz ----------------------------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############SHIFTER Video Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8201|byte |Video screen memory position (High byte) |R/W<br /> $FF8203|byte |Video screen memory position (Mid byte) |R/W<br /> $FF820D|byte |Video screen memory position (Low byte) |R/W (STe)<br /> $FF8205|byte |Video address pointer (High byte) |R (R/W STe)<br /> $FF8207|byte |Video address pointer (Mid byte) |R (R/W STe)<br /> $FF8209|byte |Video address pointer (Low byte) |R (R/W STe)<br /> $FF820E|word |Offset to next line |R/W (F030)<br /> $FF820F|byte |Width of a scanline (width in words-1) |R/W (STe)<br /> $FF8210|word |Width of a scanline (width in words) |R/W (F030)<br /> $FF8264|byte |Horizontal scroll register without prefetch (0-15) |R/W (STe)<br /> $FF8265|byte |Horizontal scroll register with prefetch (0-15) |R/W (STe)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF820A|byte |Video synchronization mode BIT 1 0|R/W<br /> | |0 - 60hz, 1 - 50hz -------------------------------+ ||<br /> | |0 - internal, 1 - external sync ------------------' || (TT)<br /> | |0 - internal, 1 - external sync --------------------'| (!TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> | | BIT 11111198 76543210|<br /> | | 543210 |<br /> | | ST color value .....RRr .GGr.BBb|<br /> | | STe color value ....rRRR gGGGbBBB|<br /> $FF8240|word |Video palette register 0 Lowercase = LSB|R/W<br /> : | : | : : : : | :<br /> $FF825E|word |Video palette register 15 |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8260|byte |Shifter resolution BIT 1 0|R/W<br /> | |00 320x200x4 bitplanes (16 colors) ---------------+-+|<br /> | |01 640x200x2 bitplanes (4 colors) ----------------+-+|<br /> | |10 640x400x1 bitplane (1 colors) ----------------+-'|<br /> $FF8262|word |TT Shifter resolution BIT 15 . . 12|R/W (TT)<br /> | |Sample/Hold mode ----------------------------' ||<br /> | |Hypermono mode -------------------------------------'|<br /> | |Video Mode BIT 10 9 8|<br /> | |000 320x200x4 bitplanes (16 colors) -----------+-+-+|<br /> | |001 640x200x2 bitplanes (4 colors) ------------+-+-+|<br /> | |010 640x400x1 bitplane (2 colors)(Duochrome) -+-+-+|<br /> | |100 640x480x4 bitplanes (16 colors) -----------+-+-+|<br /> | |110 1280x960x1 bitplane (2 colors) ------------+-+-+|<br /> | |111 320x480x8 bitplanes (256 colors) ----------+-+-'|<br /> | |ST Palette Bank BIT 3 2 1 0|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF827E|word |STACY Display Driver BIT 10 9|R/W(STACY)<br /> | |Backlight on/off ---------------------------------+ ||<br /> | |Display on/off -------------------------------------+| <br /> -------+-----+-----------------------------------------------------+----------<br /> | | BIT 11111198 76543210|<br /> | | 543210 |<br /> | | TT color value ....RRRr GGGgBBBb|<br /> $FF8400|word |TT Palette 0 Lowercase = LSB|R/W (TT)<br /> : | : | : : : | : :<br /> $FF85FE|word |TT Palette 255 |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon030 VIDEL Video Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8006|byte |Monitor Type BIT 7 6 5 4 3 2 1 0|R (F030)<br /> | |Monitor Type (M0,M1) -----------------+-+ | | | | | ||<br /> | |00 - Monochrome (SM124) --------------+-+ | | | | | ||<br /> | |01 - RGB (SC1224) --------------------+-+ | | | | | ||<br /> | |10 - VGA Color -----------------------+-+ | | | | | ||<br /> | |11 - Television ----------------------+-+ | | | | | ||<br /> | |ST-RAM size ------------------------------+-+ | | | ||<br /> | | 00 = 1MB -------------------------------+-+ | | | ||<br /> | | 01 = 4MB -------------------------------+-+ | | | ||<br /> | | 10 = 16MB ------------------------------+-+ | | | ||<br /> | |ROM Wait Status ------------------------------+ + | ||<br /> | | 00 = Reserved ------------------------------+ + | ||<br /> | | 01 = 2 Wait (default) ----------------------+ + | ||<br /> | | 10 = 1 Wait --------------------------------+ + | ||<br /> | | 11 = 0 Wait --------------------------------+ + | ||<br /> | |Video bus width ----------------------------------+ ||<br /> | | 0 = 16 Bit, -----------------------------------+ ||<br /> | | 1 = 32 Bit (default) ---------------------------+ ||<br /> | |RAM Wait Status ------------------------------------+|<br /> | | 0 = 1 Wait (default) ----------------------------+|<br /> | | 1 = 0 Wait --------------------------------------+|<br /> $FF820E|word |Offset to next line |R/W (F030)<br /> $FF8210|word |VWRAP - Linewidth in words |R/W (F030)<br /> $FF8266|word |SPSHIFT BIT 10 9 8 . 6 5 4 3 2 1 0|R/W (F030)<br /> | |2-colour mode ------------------' | | | | | | | | ||<br /> | |Overlay mode ---------------------' | | | | | | | ||<br /> | |Truecolour mode --------------------' | | | | | | ||<br /> | |Use external Hsync (1 - on) ------------' | | | | | ||<br /> | |Use external Vsync (1 - on) --------------' | | | | ||<br /> | |8 Bitplane mode ----------------------------' | | | ||<br /> | |Color Palette Bank from 256 colors (0-15) ----+-+-+-+|<br /> | +-----------------------------------------------------+<br /> | | Horizontal Control Registers (BIT 9-0)|<br /> $FF8280|word |HHC - Horizontal Hold Counter |R (F030)<br /> $FF8282|word |HHT - Horizontal Hold Timer |R/W (F030)<br /> $FF8284|word |HBB - Horizontal Border Begin |R/W (F030)<br /> $FF8286|word |HBE - Horizontal Border End |R/W (F030)<br /> $FF8288|word |HDB - Horizontal Display Begin |R/W (F030)<br /> $FF828A|word |HDE - Horizontal Display End |R/W (F030)<br /> $FF828C|word |HSS - Horizontal SS |R/W (F030)<br /> $FF828E|word |HFS - Horizontal FS |R/W (F030)<br /> $FF8290|word |HEE - Horizontal EE |R/W (F030)<br /> | +-----------------------------------------------------+<br /> | | Vertical Control Registers (BIT 10-0)| <br /> $FF82A0|word |VFC - Vertcial Frequency Counter |R (F030)<br /> $FF82A2|word |VFT - Vertical Frequency Timer |R/W (F030)<br /> $FF82A4|word |VBB - Vertical Border Begin (count in 1/2 lines)|R/W (F030)<br /> $FF82A6|word |VBE - Vertical Border End (count in 1/2 lines)|R/W (F030)<br /> $FF82A8|word |VDB - Vertical Display Begin |R/W (F030)<br /> $FF82AA|word |VDE - Vertical Display End |R/W (F030)<br /> $FF82AC|word |VSS - Vertical SS |R/W (F030)<br /> | +-----------------------------------------------------+<br /> $FF82C0|word |Video Control (VCO) (Super78 puts $182 here) |R/W (F030)<br /> | | BIT 8 7 6 5 . 3 2 1 0|<br /> | |Hz base offset ---------------------' | | | | | | ||<br /> | | 0: 128 cycles --------------------' | | | | | | ||<br /> | | (ST Low/Mid on RGB | | | | | | ||<br /> | | and ST Hi on SM124) | | | | | | ||<br /> | | 1: 64 cycles (all the others) ---' | | | | | | ||<br /> | |Videobus width -----------------------' | | | | | ||<br /> | | 0: 16 Bit-Videobus -----------------' | | | | | ||<br /> | | 1: 32 Bit-Videobus (Falcon) --------' | | | | | ||<br /> | |HSync-Impulse --------------------------' | | | | ||<br /> | | 0: negative HSync-Impulse (5V &gt; 0V) --' | | | | ||<br /> | | 1: positive HSync-Impulse (0V &gt; 5V) --' | | | | ||<br /> | |VSync-Impulse ----------------------------' | | | ||<br /> | | 0: negative VSync-Impulse (5V &gt; 0V) ----' | | | ||<br /> | | 1: positive VSync-Impulse (0V &gt; 5V) ----' | | | ||<br /> | |Half-line-HSyncs------------------------------' | | ||<br /> | | 0: No Half-line-HSyncs ---------------------' | | ||<br /> | | 1: 15 Half-line-HSyncs from start of -------' | | ||<br /> | |Video base clock -------------------------------' | ||<br /> | | 0: Video base clock 32 MHz -------------------' | ||<br /> | | 1: Video base clock 25.175 MHz ---------------' | ||<br /> | |Monitor Type (M0,M1 same as bit 7&amp;6 in $FF0006) --+-+|<br /> | | 00 - Monochrome (SM124) ------------------------+-+|<br /> | | 01 - RGB (SC1224) ------------------------------+-+|<br /> | | 10 - VGA Color ---------------------------------+-+|<br /> | | 11 - Television --------------------------------+-+|<br /> $FF82C2|word |Video Mode (VDM) BIT 3 2 1 0|R/W (F030)<br /> | |Pixel width ----------------------------------+-+ | ||<br /> | | 00: 4 cycles/pixel -------------------------+-+ | ||<br /> | | 01: 2 cycles/pixel -------------------------+-+ | ||<br /> | | 10: 1 cycle/pixel -------------------------+-+ | ||<br /> | | 11: n/a -------------------------+-+ | ||<br /> | |Skip line (interlace) (1-on) ---------------------' ||<br /> | |Double lines (1-on) --------------------------------'| <br /> -------+-----+-----------------------------------------------------+----------<br /> ##############DMA/WD1772 Disk controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8600| |Reserved |<br /> $FF8602| |Reserved |<br /> $FF8604|word |FDC access/sector count |R/W<br /> $FF8606|word |DMA mode/status BIT 2 1 0|R<br /> | |Condition of FDC DATA REQUEST signal -----------' | ||<br /> | |0 - sector count null,1 - not null ---------------' ||<br /> | |0 - no error, 1 - DMA error ------------------------'|<br /> $FF8606|word |DMA mode/status BIT 8 7 6 . 4 3 2 1 .|W<br /> | |0 - read FDC/HDC,1 - write ---------' | | | | | | | |<br /> | |0 - HDC access,1 - FDC access --------' | | | | | | |<br /> | |0 - DMA on,1 - no DMA ------------------' | | | | | |<br /> | |Reserved ---------------------------------' | | | | |<br /> | |0 - FDC reg,1 - sector count reg -----------' | | | |<br /> | |0 - FDC access,1 - HDC access ----------------' | | |<br /> | |0 - pin A1 low, 1 - pin A1 high ----------------' | |<br /> | |0 - pin A0 low, 1 - pin A0 high ------------------' |<br /> $FF8609|byte |DMA base and counter (High byte) |R/W<br /> $FF860B|byte |DMA base and counter (Mid byte) |R/W<br /> $FF860D|byte |DMA base and counter (Low byte) |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############TT-SCSI DMA Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8701|byte |DMA Address Pointer (Highest byte) |R/W (TT)<br /> $FF8703|byte |DMA Address Pointer (High byte) |R/W (TT)<br /> $FF8705|byte |DMA Address Pointer (Low byte) |R/W (TT)<br /> $FF8707|byte |DMA Address Pointer (Lowest byte) |R/W (TT)<br /> $FF8709|byte |DMA Byte Count (Highest byte) |R/W (TT)<br /> $FF870B|byte |DMA Byte Count (High byte) |R/W (TT)<br /> $FF870D|byte |DMA Byte Count (Low byte) |R/W (TT)<br /> $FF870F|byte |DMA Byte Count (Lowest byte) |R/W (TT)<br /> $FF8710|word |Residue Data Register (High Word) |R (TT)<br /> $FF8712|word |Residue Data Register (Low Word) |R (TT)<br /> $FF8715|byte |Control register BIT 7 6 . . . . 1 0|R/W (TT)<br /> | |Bus error ----------------------------' | | ||<br /> | |Byte count zero ------------------------' | ||<br /> | |Enable -------------------------------------------' ||<br /> | |DMA Direction (1 - out to port) --------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############TT-SCSI Drive Controller NCR 5380 ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8781|byte |Data register |R/W (TT)<br /> $FF8783|byte |Init-Command Register |R/W (TT)<br /> $FF8785|byte |Mode Register |R/W (TT)<br /> $FF8787|byte |Target-Command Register |R/W (TT)<br /> $FF8789|byte |ID Select/SCSI Control Register |R/W (TT)<br /> $FF878B|byte |Status Register |R/W (TT)<br /> $FF878D|byte |Target Receive/Input Data |R/W (TT)<br /> $FF878F|byte |Initiate Receive/Reset |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############YM2149 Sound Chip ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8800|byte |Read data/Register select |R/W<br /> | |0 Channel A Freq Low BIT 7 6 5 4 3 2 1 0|<br /> | |1 Channel A Freq High BIT 3 2 1 0|<br /> | |2 Channel B Freq Low BIT 7 6 5 4 3 2 1 0|<br /> | |3 Channel B Freq High BIT 3 2 1 0|<br /> | |4 Channel C Freq Low BIT 7 6 5 4 3 2 1 0|<br /> | |5 Channel C Freq High BIT 3 2 1 0|<br /> | |6 Noise Freq BIT 5 4 3 2 1 0|<br /> | |7 Mixer Control BIT 7 6 5 4 3 2 1 0|<br /> | | Port B IN/OUT (1=Output) -----------' | | | | | | ||<br /> | | Port A IN/OUT ------------------------' | | | | | ||<br /> | | Channel C Noise (1=Off) ----------------' | | | | ||<br /> | | Channel B Noise --------------------------' | | | ||<br /> | | Channel A Noise ----------------------------' | | ||<br /> | | Channel C Tone (0=On) ------------------------' | ||<br /> | | Channel B Tone ---------------------------------' ||<br /> | | Channel A Tone -----------------------------------'|<br /> | |8 Channel A Amplitude Control BIT 4 3 2 1 0|<br /> | | Fixed/Variable Level (0=Fixed) -----------' | | | ||<br /> | | Amplitude level control --------------------+-+-+-'|<br /> | |9 Channel B Amplitude Control BIT 4 3 2 1 0|<br /> | | Fixed/Variable Level ---------------------' | | | ||<br /> | | Amplitude level control --------------------+-+-+-'|<br /> | |10 Channel C Amplitude Control BIT 4 3 2 1 0|<br /> | | Fixed/Variable Level ---------------------' | | | ||<br /> | | Amplitude level control --------------------+-+-+-'|<br /> | |11 Envelope Period High BIT 7 6 5 4 3 2 1 0|<br /> | |12 Envelope Period Low BIT 7 6 5 4 3 2 1 0|<br /> | |13 Envelope Shape BIT 3 2 1 0|<br /> | | Continue -----------------------------------' | | ||<br /> | | Attack ---------------------------------------' | ||<br /> | | Alternate --------------------------------------' ||<br /> | | Hold ---------------------------------------------'|<br /> | | 00xx - \____________________________________ |<br /> | | 01xx - /|___________________________________ |<br /> | | 1000 - \|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\ |<br /> | | 1001 - \____________________________________ |<br /> | | 1010 - \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ |<br /> | | 1011 - \|----------------------------------- |<br /> | | 1100 - /|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/ |<br /> | | 1101 - /------------------------------------ |<br /> | | 1110 - /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ |<br /> | | 1111 - /|___________________________________ |<br /> | |14 Port A BIT 7 6 5 4 3 2 1 0|<br /> | | IDE Drive On/OFF -------------------+ | | | | | | || (F030)<br /> | | SCC A (0=LAN, 1=Serial2) -----------' | | | | | | || (TT)<br /> | | Monitor jack GPO pin -----------------+ | | | | | ||<br /> | | Internal Speaker On/Off --------------' | | | | | || (F030)<br /> | | Centronics strobe ----------------------' | | | | ||<br /> | | RS-232 DTR output ------------------------' | | | ||<br /> | | RS-232 RTS output --------------------------' | | ||<br /> | | Drive select 1 -------------------------------' | ||<br /> | | Drive select 0 ---------------------------------' ||<br /> | | Drive side select --------------------------------'|<br /> | |15 Port B (Parallel port) |<br /> $FF8802|byte |Write data |W<br /> | +-----------------------------------------------------+<br /> | |Note: PSG Registers are now fixed at these addresses.|<br /> | |All other addresses are masked out on the Falcon. Any|<br /> | |writes to the shadow registers $8804-$88FF will cause|<br /> | |bus errors. Game/Demo coders beware! |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############DMA Sound System ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8900|byte |Buffer interrupts BIT 3 2 1 0|R/W (F030)<br /> | |TimerA-Int at end of record buffer -----------' | | ||<br /> | |TimerA-Int at end of replay buffer -------------' | ||<br /> | |MFP-15-Int (I7) at end of record buffer ----------' ||<br /> | |MFP-15-Int (I7) at end of replay buffer ------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8901|byte |DMA Control Register BIT 7 . 5 4 . . 1 0|R/W<br /> | |1 - select record register -----------+ | | | || (F030) <br /> | |0 - select replay register -----------' | | | || (F030)<br /> | |Loop record buffer -----------------------' | | || (F030)<br /> | |DMA Record on ------------------------------' | || (F030)<br /> | |Loop replay buffer -------------------------------' || (STe)<br /> | |DMA Replay on --------------------------------------'| (STe)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8903|byte |Frame start address (high byte) |R/W (STe)<br /> $FF8905|byte |Frame start address (mid byte) |R/W (STe)<br /> $FF8907|byte |Frame start address (low byte) |R/W (STe)<br /> $FF8909|byte |Frame address counter (high byte) |R (STe)<br /> $FF890B|byte |Frame address counter (mid byte) |R (STe)<br /> $FF890D|byte |Frame address counter (low byte) |R (STe)<br /> $FF890F|byte |Frame end address (high byte) |R/W (STe)<br /> $FF8911|byte |Frame end address (mid byte) |R/W (STe)<br /> $FF8913|byte |Frame end address (low byte) |R/W (STe)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8920|byte |DMA Track Control BIT 5 4 . . 1 0|R/W (F030)<br /> | |00 - Set DAC to Track 0 ------------------+-+ | ||<br /> | |01 - Set DAC to Track 1 ------------------+-+ | ||<br /> | |10 - Set DAC to Track 2 ------------------+-+ | ||<br /> | |11 - Set DAC to Track 3 ------------------+-' | ||<br /> | |00 - Play 1 Track --------------------------------+-+|<br /> | |01 - Play 2 Tracks -------------------------------+-+|<br /> | |10 - Play 3 Tracks -------------------------------+-+|<br /> | |11 - Play 4 Tracks -------------------------------+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8921|byte |Sound mode control BIT 7 6 . . . . 1 0|R/W (STe)<br /> | |0 - Stereo, 1 - Mono -----------------' | | ||<br /> | |0 - 8bit -------------------------------+ | ||<br /> | |1 - 16bit (F030 only) ------------------' | || (F030)<br /> | |Frequency control bits | ||<br /> | |00 - Off (F030 only) -----------------------------+-+| (F030)<br /> | |00 - 6258hz frequency (STe only) -----------------+-+|<br /> | |01 - 12517hz frequency ---------------------------+-+|<br /> | |10 - 25033hz frequency ---------------------------+-+|<br /> | |11 - 50066hz frequency ---------------------------+-'|<br /> | |Samples are always signed. In stereo mode, data is |<br /> | |arranged in pairs with high pair the left channel,low|<br /> | |pair right channel. Sample length MUST be even in |<br /> | |either mono or stereo mode. |<br /> | |Example: 8 bit Stereo : LRLRLRLRLRLRLRLR |<br /> | | 16 bit Stereo : LLRRLLRRLLRRLLRR (F030) |<br /> | |2 track 16 bit stereo : LLRRllrrLLRRllrr (F030) |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############STe Microwire Controller (STe/TT only!) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8922|byte |Microwire data register |R/W (Mwr)<br /> $FF8924|byte |Microwire mask register |R/W (Mwr)<br /> | +-----------------------------------------------------+<br /> | |!! ATTENTION !! Microwire is now obsolete! It is not |<br /> | |present in the Falcon030 and is unlikely to be in any|<br /> | |future machines. You have been warned. | <br /> | +-----------------------------------------------------+<br /> | |Volume/tone controller commands (Address %10)|<br /> | |Master Volume 10 011 DDDDDD|<br /> | |Left Volume 10 101 .DDDDD|<br /> | |Right Volume 10 100 .DDDDD|<br /> | |Treble 10 010 ..DDDD|<br /> | |Bass 10 001 ..DDDD|<br /> | |Mixer 10 000 ....DD|<br /> | +-----------------------------------------------------+<br /> | |Volume/tone controller values |<br /> | |Master Volume : 0-40 (0 = -80dB, 40 = 0dB) |<br /> | |Left/Right Volume : 0-20 (0 = -40dB, 20 = 0dB) |<br /> | |Treble/bass : 0-12 (0 = -12dB, 12 = +12dB) |<br /> | |Mixer : 0-3: |<br /> | | 0 = DMA only |<br /> | | 1 = DMA + YM2149 |<br /> | | 2 = DMA only |<br /> | | 3 = reserved |<br /> | | (there is no DMA + (YM2149 - 12dB) mode!) |<br /> | +-----------------------------------------------------+<br /> | |Procedure: Set mask register to $7ff. Read data |<br /> | |register and save original value.Write data register.|<br /> | |Compare data register with original value, repeat |<br /> | |until data register returns to original value to |<br /> | |ensure data has been sent over the interface. |<br /> | +-----------------------------------------------------+<br /> | |Interrupts: Timer A can be set to interrupt at the |<br /> | |end of a frame. Alternatively, the GPI7 (MFP mono |<br /> | |detect) can be used to generate interrupts thereby |<br /> | |freeing up Timer A. In this case, the active edge |<br /> | |$FFFA03 must be set by or-ing the active edge of |<br /> | |$FFFA03 with the contents of $FF8260: |<br /> | |$FF8260 - 2 (mono) or.b #$80 with edge |<br /> | |$FF8260 - 0,1 (colour) and.b #$7F with edge |<br /> | |This will generate an interrupt at the START of a |<br /> | |frame, instead of at the end as with Timer A. To |<br /> | |generate an interrupt at the END of a frame, simply |<br /> | |reverse the edge values. |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon030 DMA/DSP Controllers ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8930|word |Crossbar Source Controller |R/W (F030)<br /> | +-----------------------------------------------------+<br /> | |Source: A/D Convertor BIT 15 14 13 12|<br /> | |1 - Connect, 0 - disconnect ---------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock (Don't use) -----------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Source: External Input BIT 11 10 9 8|<br /> | |0 - DSP IN, 1 - All others ----------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock -----------------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Source: DSP-XMIT BIT 7 6 5 4|<br /> | |0 - Tristate and disconnect DSP -----------+ | | ||<br /> | | (Only for external SSI use) | | | ||<br /> | |1 - Connect DSP to multiplexer ------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock -----------------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Source: DMA-PLAYBACK BIT 3 2 1 0|<br /> | |0 - Handshaking on, dest DSP-REC ----------+ | | ||<br /> | |1 - Destination is not DSP-REC ------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock -----------------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8932|word |Crossbar Destination Controller |R/W (F030)<br /> | +-----------------------------------------------------+<br /> | |Destination: D/A Convertor BIT 15 14 13 12|<br /> | |1 - Connect, 0 - Disconnect ---------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Destination: External Output BIT 11 10 9 8|<br /> | |0 - DSP out, 1 - All others ---------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Destination: DSP-RECORD BIT 7 6 5 4|<br /> | |0 - Tristate and disconnect DSP -----------+ | | ||<br /> | | (Only for external SSI use) | | | ||<br /> | |1 - Connect DSP to multiplexer ------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Destination: DMA-RECORD BIT 3 2 1 0|<br /> | |0 - Handshaking on, src DSP-XMIT ----------+ | | ||<br /> | |1 - Source is not DSP-XMIT ----------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8934|byte |Frequency Divider External Clock BIT 3 2 1 0|R/W (F030)<br /> | |0000 - STe-Compatible mode |<br /> | |0001 - 1111 Divide by 256 and then number |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8935|byte |Frequency Divider Internal Sync BIT 3 2 1 0|R/W (F030)<br /> | |0000 - STe-Compatible mode 1000 - 10927Hz* |<br /> | |0001 - 49170Hz 1001 - 9834Hz |<br /> | |0010 - 32780Hz 1010 - 8940Hz* |<br /> | |0011 - 24585Hz 1011 - 8195Hz |<br /> | |0100 - 19668Hz 1100 - 7565Hz* |<br /> | |0101 - 16390Hz 1101 - 7024Hz* |<br /> | |0110 - 14049Hz* 1110 - 6556Hz* |<br /> | |0111 - 12292Hz 1111 - 6146Hz* |<br /> | | * - Invalid for CODEC |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8936|byte |Record Tracks Select BIT 1 0|R/W (F030)<br /> | |00 - Record 1 Track ------------------------------+-+|<br /> | |01 - Record 2 Tracks -----------------------------+-+|<br /> | |10 - Record 3 Tracks -----------------------------+-+|<br /> | |11 - Record 4 Tracks -----------------------------+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8937|byte |CODEC Input Source from 16bit adder BIT 1 0|R/W (F030)<br /> | |Source: Multiplexer ------------------------------' ||<br /> | |Source: A/D Convertor ------------------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8938|byte |CODEC ADC-Input for L+R Channel BIT 1 0|R/W (F030)<br /> | |0 - Microphone, 1 - Soundchip L R|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8939|byte |Channel amplification BIT LLLL RRRR|R/W (F030)<br /> | | Amplification is in +1.5dB steps |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF893A|word |Channel attenuation BIT LLLL RRRR|R/W (F030)<br /> | | Attenuation is in -1.5dB steps |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF893C|byte |CODEC-Status BIT 1 0|R/W (F030)<br /> | |Left Channel Overflow ----------------------------' ||<br /> | |Right Channel Overflow -----------------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8941|byte |GPx Data Direction BIT 2 1 0|R/W (F030)<br /> | |0 - In, 1 - Out --------------------------------+-+-'|<br /> | | For the GP0-GP2 pins on the DSP connector |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8943|byte |GPx Data Port BIT 2 1 0|R/W (F030)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############TT Clock Chip (MC146818A @ 32.768 khz) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8961|byte |Register select |W (TT)<br /> | |0 - Current Second |<br /> | |1 - Second for alarm |<br /> | |2 - Current Minute |<br /> | |3 - Minute for alarm |<br /> | |4 - Current Hour |<br /> | |5 - Hour for alarm |<br /> | |6 - Day of week (1=Sunday, 2=Monday, 3=...) |<br /> | |7 - Day of Month |<br /> | |8 - Month |<br /> | |9 - Year (example : '93' for this year) |<br /> | |A BIT 7|<br /> | | If set, update time in progress ----------------'|<br /> | | don't read time &amp; date registers |<br /> | |B BIT 7 6 5 4 3 2 1 0|<br /> | |1 = Write Protect time &amp; date --------' | | | | ||<br /> | |1 = Enable alarm interrupt ---------------' | | | ||<br /> | |1 = Interrupt after time updated -----------' | | ||<br /> | |1 = Format Binary, 0 = Format BCD --------------' | ||<br /> | |1 = 24hr format, 0 = 12hr format -----------------' ||<br /> | |1 = Summer hours, 0 = Winter hours -----------------'|<br /> | |C BIT 6 5 4|<br /> | | ??? -------------------------------------------' | ||<br /> | |1 = alarm is ringing -----------------------------' ||<br /> | |1 = date is updated --------------------------------'|<br /> | |On interrupt, read this register to determine source.|<br /> | |D BIT 7|<br /> | |1 = Battery dead -----------------------------------'|<br /> $FF8963|byte |Register data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Blitter (Not present on TT!) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8A00|word |Halftone-RAM, Word 0 |R/W (Blit)<br /> : | : | : : : : | : :<br /> $FF8A1E|word |Halftone-RAM, Word 15 |R/W (Blit)<br /> $FF8A20|word |Source X Increment (signed,even)|R/W (Blit)<br /> $FF8A22|word |Source Y Increment (signed,even)|R/W (Blit)<br /> $FF8A24|long |Source Address Register (24 bit,even)|R/W (Blit)<br /> $FF8A28|word |Endmask 1 (First write of a line)|R/W (Blit)<br /> $FF8A2A|word |Endmask 2 (All other line writes)|R/W (Blit)<br /> $FF8A2C|word |Endmask 3 (Last write of a line)|R/W (Blit)<br /> $FF8A2E|word |Destination X Increment (signed,even)|R/W (Blit)<br /> $FF8A30|word |Destination Y Increment (signed,even)|R/W (Blit)<br /> $FF8A32|long |Destination Address Register (24 bit,even)|R/W (Blit)<br /> $FF8A36|word |Words per Line in Bit-Block (0=65536)|R/W (Blit)<br /> $FF8A38|word |Lines per Bit-Block (0=65536)|R/W (Blit)<br /> $FF8A3A|byte |Halftone Operation Register BIT 1 0|R/W (Blit)<br /> | |00 - All ones ------------------------------------+-+|<br /> | |01 - Halftone ------------------------------------+-+|<br /> | |10 - Source --------------------------------------+-+|<br /> | |11 - Source AND Halftone -------------------------+-'|<br /> $FF8A3B|byte |Logical Operation Register BIT 3 2 1 0|R/W (Blit)<br /> | |0000 All zeros -------------------------------+-+-+-+|<br /> | |0001 Source AND destination ------------------+-+-+-+|<br /> | |0010 Source AND NOT destination --------------+-+-+-+|<br /> | |0011 Source ----------------------------------+-+-+-+|<br /> | |0100 NOT source AND destination --------------+-+-+-+|<br /> | |0101 Destination -----------------------------+-+-+-+|<br /> | |0110 Source XOR destination ------------------+-+-+-+|<br /> | |0111 Source OR destination -------------------+-+-+-+|<br /> | |1000 NOT source AND NOT destination ----------+-+-+-+|<br /> | |1001 NOT source XOR destination --------------+-+-+-+|<br /> | |1010 NOT destination -------------------------+-+-+-+|<br /> | |1011 Source OR NOT destination ---------------+-+-+-+|<br /> | |1100 NOT source ------------------------------+-+-+-+|<br /> | |1101 NOT source OR destination ---------------+-+-+-+|<br /> | |1110 NOT source OR NOT destination -----------+-+-+-+|<br /> | |1111 All ones --------------------------------+-+-+-'|<br /> $FF8A3C|byte |Line Number Register BIT 7 6 5 . 3 2 1 0|R/W (Blit)<br /> | |BUSY ---------------------------------' | | | | | ||<br /> | |0 - Share bus, 1 - Hog bus -------------' | | | | ||<br /> | |SMUDGE mode ------------------------------' | | | ||<br /> | |Halftone line number -------------------------+-+-+-'|<br /> $FF8A3D|byte |SKEW Register BIT 7 6 . . 3 2 1 0|R/W (Blit)<br /> | |Force eXtra Source Read --------------' | | | | ||<br /> | |No Final Source Read -------------------' | | | ||<br /> | |Source skew ----------------------------------+-+-+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############SCC-DMA (TT Only!) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8C01|byte |DMA Address Pointer (Highest Byte) |R/W (TT)<br /> $FF8C03|byte |DMA Address Pointer (High Byte) |R/W (TT)<br /> $FF8C05|byte |DMA Address Pointer (Low Byte) |R/W (TT)<br /> $FF8C07|byte |DMA Address Pointer (Lowest Byte) |R/W (TT)<br /> $FF8C09|byte |DMA Byte Count (Highest-Byte) |R/W (TT)<br /> $FF8C0B|byte |DMA Byte Count (High-Byte) |R/W (TT)<br /> $FF8C0D|byte |DMA Byte Count (Low-Byte) |R/W (TT)<br /> $FF8C0F|byte |DMA Byte Count (Lowest-Byte) |R/W (TT)<br /> $FF8C10|word |Residue Data Register (High-Word) |R (TT)<br /> $FF8C12|word |Residue Data register (Low-Word) |R (TT)<br /> $FF8C15|byte |Control register BIT 7 6 . . . . 1 0|R/W (TT)<br /> | |Bus error ----------------------------' | | ||<br /> | |Byte count zero ------------------------' | ||<br /> | |Enable -------------------------------------------' ||<br /> | |DMA Direction (1 - out to port) --------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Zilog 8530 SCC (MSTe/TT/F030) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8C81|byte |Channel A - Control Register |R/W (SCC)<br /> $FF8C83|byte |Channel A - Data Register |R/W (SCC)<br /> $FF8C85|byte |Channel B - Control Register |R/W (SCC)<br /> $FF8C87|byte |Channel B - Data Register |R/W (SCC)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############VME Bus System Control Unit (MSTe/TT) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E01|byte |VME sys_mask BIT 7 6 5 4 . 2 1 .|R/W (VME)<br /> $FF8E03|byte |VME sys_stat BIT 7 6 5 4 . 2 1 .|R (VME)<br /> | |_SYSFAIL in VMEBUS -------------------' | | | | | |program<br /> | |MFP ------------------------------------' | | | | |autovec<br /> | |SCC --------------------------------------' | | | |autovec<br /> | |VSYNC --------------------------------------' | | |program<br /> | |HSYNC ------------------------------------------' | |program<br /> | |System software INT ------------------------------' |program<br /> | +-----------------------------------------------------+<br /> | |Reading sys_mask resets pending int-bits in sys_stat,|<br /> | |so read sys_stat first. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E05|byte |VME sys_int BIT 0|R/W (VME)<br /> | |Setting bit 0 to 1 forces an INT of level 1. INT must|Vector $64<br /> | |be enabled in sys_mask to use it. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E0D|byte |VME vme_mask BIT 7 6 5 4 3 2 1 .|R/W (VME)<br /> $FF8E0F|byte |VME vme_stat BIT 7 6 5 4 3 2 1 .|R (VME)<br /> | |_IRQ7 from VMEBUS --------------------' | | | | | | |program<br /> | |_IRQ6 from VMEBUS/MFP ------------------' | | | | | |program<br /> | |_IRQ5 from VMEBUS/SCC --------------------' | | | | |program<br /> | |_IRQ4 from VMEBUS --------------------------' | | | |program<br /> | |_IRQ3 from VMEBUS/soft -----------------------' | | |prog/autov<br /> | |_IRQ2 from VMEBUS ------------------------------' | |program<br /> | |_IRQ1 from VMEBUS --------------------------------' |program<br /> | +-----------------------------------------------------+<br /> | |MFP-int and SCC-int are hardwired to the VME-BUS-ints|<br /> | |(or'ed). Reading vme_mask resets pending int-bits in |<br /> | |vme_stat, so read vme_stat first. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E07|byte |VME vme_int BIT 0|R/W (TT)<br /> | |Setting bit 0 to 1 forces an INT of level 3. INT must|Vector $6C<br /> | |be enabled in vme_mask to use it. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E09|byte |General purpose register - does nothing |R/W (TT)<br /> $FF8E0B|byte |General purpose register - does nothing |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Mega STe Cache/Processor Control ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E21|byte |Mega STe Cache/Processor Control BIT 15-1 0|R/W (MSTe)<br /> | |Cache enable lines (set all to 1 to enable) -----' ||<br /> | |CPU Speed (0 - 8mhz, 1 - 16mhz) --------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############DIP Switches (MSTe/TT) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF9200|byte |DIP Switches (MSTe/TT) BIT 7 6 5 4 3 2 1 0|R (MSTe/TT)<br /> | |Sound DMA active ---------------------' | ||<br /> | |Floppy Drive 1.44 HD active ------------' ||<br /> | |CaTTamaran installed -------------------------------'|<br /> | | |<br /> | |That register is mirrored by the OS in &quot;_SWI&quot; Cookie |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############STe/F030 Extended Joystick/Lightpen Ports ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF9200|word |Fire buttons 1-4 Bit 3 2 1 0|R (Ext)<br /> | |Pause/F0 -------------------------------------' | | ||<br /> | |F1 ---------------------------------------------' | ||<br /> | |F2 -----------------------------------------------' ||<br /> | |Option/F3 ------------------------------------------'|<br /> $FF9202|word |Read Mask (0 - pin read) |W (Ext)<br /> $FF9202|word |Joystick Inputs BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> | |Controller 1 pin 4 -------------------' | | | | | | ||<br /> | |Controller 1 pin 3 ---------------------' | | | | | ||<br /> | |Controller 1 pin 2 -----------------------' | | | | ||<br /> | |Controller 1 pin 1 -------------------------' | | | ||<br /> | |Controller 0 pin 4 ---------------------------' | | ||<br /> | |Controller 0 pin 3/Paddle 1 Trigger ------------' | ||<br /> | |Controller 0 pin 2/Paddle 0 Trigger --------------' ||<br /> | |Controller 0 pin 1 ---------------------------------'|<br /> | | BIT 15 14 13 12 11 10 9 8|<br /> | |Controller 1 pin 14 ------------' | | | | | | ||<br /> | |Controller 1 pin 13 ----------------' | | | | | ||<br /> | |Controller 1 pin 12 -------------------' | | | | ||<br /> | |Controller 1 pin 11 ----------------------' | | | ||<br /> | |Controller 0 pin 14 -------------------------' | | ||<br /> | |Controller 0 pin 13 ----------------------------' | ||<br /> | |Controller 0 pin 12 ------------------------------' ||<br /> | |Controller 0 pin 11 --------------------------------'|<br /> $FF9210|word |X Paddle 0 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9212|word |Y Paddle 0 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9214|word |X Paddle 1 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9216|word |Y Paddle 1 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9220|word |Lightpen X-Position BIT 9 8 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9222|word |Lightpen Y-Position BIT 9 8 7 6 5 4 3 2 1 0|R (Ext)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon VIDEL Palette Registers ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> | | BIT 33222222 22221111 11111198 76543210|<br /> | | 10987654 32109876 543210 |<br /> | | RRRRRr.. GGGGGg.. ........ BBBBBb..|<br /> $FF9800|long |Palette Register 0 Lowercase = LSB|R/W (F030)<br /> : | : | : : : | : :<br /> $FF98FC|long |Palette Register 255 |R/W (F030)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon DSP Host Interface ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFA200|byte |Interrupt Ctrl Register BIT 7 6 5 4 3 . 1 0|R/W (F030)<br /> X:$FFE9| |INIT bit -----------------------------' | | | | | ||<br /> | |00 - Interupt mode (DMA off) -----------+-+ | | | ||<br /> | |01 - 24-bit DMA mode -------------------+-+ | | | ||<br /> | |10 - 16-bit DMA mode -------------------+-+ | | | ||<br /> | |11 - 8-bit DMA mode --------------------+-' | | | ||<br /> | |Host Flag 1 --------------------------------' | | ||<br /> | |Host Flag 0 ----------------------------------' | ||<br /> | | Host mode Data transfers: | ||<br /> | | Interrupt mode | ||<br /> | |00 - No interrupts (Polling) ---------------------+-+|<br /> | |01 - RXDF Request (Interrupt) --------------------+-+|<br /> | |10 - TXDE Request (Interrupt) --------------------+-+|<br /> | |11 - RXDF and TXDE Request (Interrupts) ----------+-+|<br /> | | DMA Mode | ||<br /> | |00 - No DMA --------------------------------------+-+|<br /> | |01 - DSP to Host Request (RX) --------------------+-+|<br /> | |10 - Host to DSP Request (TX) --------------------+-+|<br /> | |11 - Undefined (Illegal) -------------------------+-'|<br /> $FFA201|byte |Command Vector Register BIT 7 . . 4 3 2 1 0|R/W (F030)<br /> X:$FFE9| |Host Command Bit (Handshake)----------' | | | | ||<br /> | |Host Vector (0-31) -------------------------+-+-+-+-'|<br /> $FFA202|byte |Interrupt Status Reg BIT 7 6 . 4 3 2 1 0|R (F030)<br /> X:$FFE8| |ISR Host Request ---------------------' | | | | | ||<br /> | |ISR DMA Status -------------------------' | | | | ||<br /> | |Host Flag 3 --------------------------------' | | | ||<br /> | |Host Flag 2 ----------------------------------' | | ||<br /> | |ISR Transmitter Ready (TRDY) -------------------' | ||<br /> | |ISR Transmit Data Register Empty (TXDE) ----------' ||<br /> | |ISR Receive Data Register Full (RXDF) --------------'|<br /> $FFA203|byte |Interrupt Vector Register |R/W (F030)<br /> $FFA204|byte |Unused | (F030)<br /> $FFA205|byte |DSP-Word High |R/W (F030)<br /> X:$FFEB| | |<br /> $FFA206|byte |DSP-Word Mid |R/W (F030)<br /> X:$FFEB| | |<br /> $FFA207|byte |DSP-Word Low |R/W (F030)<br /> X:$FFEB| | |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############MFP 68901 - Multi Function Peripheral Chip ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> | | MFP Master Clock is 2,457,600 cycles/second |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA01|byte |Parallel Port Data Register |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA03|byte |Active Edge Register BIT 7 6 5 4 . 2 1 0|R/W<br /> | |Monochrome monitor detect ------------' | | | | | | ||<br /> | |RS-232 Ring indicator ------------------' | | | | | ||<br /> | |FDC/HDC interrupt ------------------------' | | | | ||<br /> | |Keyboard/MIDI interrupt --------------------' | | | ||<br /> | |Reserved -------------------------------------' | | ||<br /> | |RS-232 CTS (input) -----------------------------' | ||<br /> | |RS-232 DCD (input) -------------------------------' ||<br /> | |Centronics busy ------------------------------------'|<br /> | +-----------------------------------------------------+<br /> | | When port bits are used for input only: |<br /> | |0 - Interrupt on pin high-low conversion |<br /> | |1 - Interrupt on pin low-high conversion |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA05|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W<br /> | |0 - In, 1 - Out ----------------------+-+-+-+-+-+-+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA07|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA0B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA0F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA13|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W<br /> | |MFP Address | | | | | | | ||<br /> | |$13C GPI7-Monochrome Detect ----------' | | | | | | ||<br /> | |$138 RS-232 Ring Detector ------------' | | | | | ||<br /> | |$134 (STe sound) Timer A --------------' | | | | ||<br /> | |$130 Receive buffer full ----------------' | | | ||<br /> | |$12C Receive error ------------------' | | ||<br /> | |$128 Send buffer empty --------------------' | ||<br /> | |$124 Send error ----------------------' ||<br /> | |$120 (HBL) Timer B ------------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA09|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA0D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA11|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA15|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W<br /> | |MFP Address | | | | | | | ||<br /> | |$11C FDC/HDC ----------' | | | | | | ||<br /> | |$118 Keyboard/MIDI ------------' | | | | | ||<br /> | |$114 (200hz clock) Timer C --------------' | | | | ||<br /> | |$110 (USART timer) Timer D ----------------' | | | ||<br /> | |$10C Blitter done ------------------' | | ||<br /> | |$108 RS-232 CTS - input --------------------' | ||<br /> | |$104 RS-232 DCD - input ----------------------' ||<br /> | |$100 Centronics Busy ------------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA17|byte |Vector Register BIT 7 6 5 4 3 . . .|R/W<br /> | |Vector Base Offset -------------------+-+-+-' | |<br /> | |1 - *Software End-interrupt mode -------------+ |<br /> | |0 - Automatic End-interrupt mode -------------' |<br /> | |* - Default operating mode |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA19|byte |Timer A Control BIT 4 3 2 1 0|R/W<br /> $FFFA1B|byte |Timer B Control BIT 4 3 2 1 0|R/W<br /> | |Reset (force output low) -------------------' | | | ||<br /> | +----------------------------------------------+-+-+-++<br /> | |0000 - Timer stop, no function executed |<br /> | |0001 - Delay mode, divide by 4 |<br /> | |0010 - : : 10 |<br /> | |0011 - : : 16 |<br /> | |0100 - : : 50 |<br /> | |0101 - : : 64 |<br /> | |0110 - : : 100 |<br /> | |0111 - Delay mode, divide by 200 |<br /> | |1000 - Event count mode |<br /> | |1xxx - Pulse extension mode, divide as above |<br /> | +-----------------------------------------------------+<br /> $FFFA1F|byte |Timer A Data |R/W<br /> $FFFA21|byte |Timer B Data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA1D|byte |Timer C &amp; D Control BIT 6 5 4 . 2 1 0|R/W<br /> | | Timer Timer|<br /> | | C D |<br /> | +-----------------------------------------------------+<br /> | |000 - Timer stop |<br /> | |001 - Delay mode, divide by 4 |<br /> | |010 - : : 10 |<br /> | |011 - : : 16 |<br /> | |100 - : : 50 |<br /> | |101 - : : 64 |<br /> | |110 - : : 100 |<br /> | |111 - Delay mode, divide by 200 |<br /> | +-----------------------------------------------------+<br /> $FFFA23|byte |Timer C Data |R/W<br /> $FFFA25|byte |Timer D Data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA27|byte |Sync Character |R/W<br /> $FFFA29|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W<br /> | |Clock divide (1 - div by 16) ---------' | | | | | | ||<br /> | |Word Length 00 - 8 bits ----------------+-+ | | | | ||<br /> | | 01 - 7 bits ----------------+-+ | | | | ||<br /> | | 10 - 6 bits ----------------+-+ | | | | ||<br /> | | 11 - 5 bits ----------------+-' | | | | ||<br /> | |Bits Stop Start Format | | | | ||<br /> | |00 0 0 Synchronous ----------------+-+ | | ||<br /> | |01 1 1 Asynchronous ---------------+-+ | | ||<br /> | |10 1 1.5 Asynchronous ---------------+-+ | | ||<br /> | |11 1 2 Asynchronous ---------------+-' | | ||<br /> | |Parity (0 - ignore parity bit) -----------------' | ||<br /> | |Parity (0 - odd parity,1 - even) -----------------' ||<br /> | |Unused ---------------------------------------------'|<br /> $FFFA2B|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W<br /> | |Buffer full --------------------------' | | | | | | ||<br /> | |Overrun error --------------------------' | | | | | ||<br /> | |Parity error -----------------------------' | | | | ||<br /> | |Frame error --------------------------------' | | | ||<br /> | |Found - Search/Break detected ----------------' | | ||<br /> | |Match/Character in progress --------------------' | ||<br /> | |Synchronous strip enable -------------------------' ||<br /> | |Receiver enable bit --------------------------------'|<br /> $FFFA2D|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W<br /> | |Buffer empty -------------------------' | | | | | | ||<br /> | |Underrun error -------------------------' | | | | | ||<br /> | |Auto turnaround --------------------------' | | | | ||<br /> | |End of transmission ------------------------' | | | ||<br /> | |Break ----------------------------------------' | | ||<br /> | |High bit ---------------------------------------' | ||<br /> | |Low bit ------------------------------------------' ||<br /> | |Transmitter enable ---------------------------------'|<br /> $FFFA2F|byte |USART data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Floating Point Coprocessor (CIR Interface in MSTe) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA40|word |FP_Stat Response-Register |??? (MSTe)<br /> $FFFA42|word |FP_Ctl Control-Register |??? (MSTe)<br /> $FFFA44|word |FP_Save Save-Register |??? (MSTe)<br /> $FFFA46|word |FP_Restor Restore-Register |??? (MSTe)<br /> $FFFA48|word | |??? (MSTe)<br /> $FFFA4A|word |FP_Cmd Command-Register |??? (MSTe)<br /> $FFFA4E|word |FP_Ccr Condition-Code-Register |??? (MSTe)<br /> $FFFA50|long |FP_Op Operand-Register |??? (MSTe)<br /> $FFFA54|word |FP_Selct Register Select |??? (MSTe)<br /> $FFFA58|long |FP_Iadr Instruction Address |??? (MSTe)<br /> $FFFA5C|long | Operand Address |??? (MSTe)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############MFP 68901 #2 (MFP2) - TT Only ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA81|byte |Parallel Port Data Register |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA83|byte |Active Edge Register BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | +-----------------------------------------------------+<br /> | | When port bits are used for input only: |<br /> | |0 - Interrupt on pin high-low conversion |<br /> | |1 - Interrupt on pin low-high conversion |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA85|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |0 - In, 1 - Out ----------------------+-+-+-+-+-+-+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA87|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA8B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA8F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA93|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |MFP Address | | | | | | | ||<br /> | |$17C TT-SCSI NCR5380 ---------' | | | | | | ||<br /> | |$178 RTC (MC146818A) -----------' | | | | | ||<br /> | |$174 Timer A -------------' | | | | ||<br /> | |$170 Receive buffer full ---------------' | | | ||<br /> | |$16C Receive error -----------------' | | ||<br /> | |$168 Send buffer empty -------------------' | ||<br /> | |$164 Send error ---------------------' ||<br /> | |$160 Timer B -----------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA89|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA8D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA91|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA95|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |MFP Address | | | | | | | ||<br /> | |$15C SCSI DMA Controller ---------' | | | | | | ||<br /> | |$158 (Reserved) GPIP 4 -----------' | | | | | ||<br /> | |$154 Timer C -------------' | | | | ||<br /> | |$150 Timer D ---------------' | | | ||<br /> | |$14C SCC B Ring Indicator -----------------' | | ||<br /> | |$148 SCC DMA Controller -------------------' | ||<br /> | |$144 General Purpose Input 1 ---------------------' ||<br /> | |$140 General Purpose Input 0 -----------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA97|byte |Vector Register BIT 7 6 5 4 3 . . .|R/W (TT)<br /> | |Vector Base Offset -------------------+-+-+-' | |<br /> | |1 - *Software End-interrupt mode -------------+ |<br /> | |0 - Automatic End-interrupt mode -------------' |<br /> | |* - Default operating mode |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA99|byte |Timer A Control BIT 4 3 2 1 0|R/W (TT)<br /> $FFFA9B|byte |Timer B Control BIT 4 3 2 1 0|R/W (TT)<br /> | |Reset (force output low) -------------------' | | | ||<br /> | +----------------------------------------------+-+-+-++<br /> | |0000 - Timer stop, no function executed |<br /> | |0001 - Delay mode, divide by 4 |<br /> | |0010 - : : 10 |<br /> | |0011 - : : 16 |<br /> | |0100 - : : 50 |<br /> | |0101 - : : 64 |<br /> | |0110 - : : 100 |<br /> | |0111 - Delay mode, divide by 200 |<br /> | |1000 - Event count mode |<br /> | |1xxx - Pulse extension mode, divide as above |<br /> | +-----------------------------------------------------+<br /> $FFFA9F|byte |Timer A Data |R/W (TT)<br /> $FFFAA1|byte |Timer B Data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA9D|byte |Timer C &amp; D Control BIT 6 5 4 . 2 1 0|R/W (TT)<br /> | | Timer Timer|<br /> | | C D |<br /> | +-----------------------------------------------------+<br /> | |000 - Timer stop |<br /> | |001 - Delay mode, divide by 4 |<br /> | |010 - : : 10 |<br /> | |011 - : : 16 |<br /> | |100 - : : 50 |<br /> | |101 - : : 64 |<br /> | |110 - : : 100 |<br /> | |111 - Delay mode, divide by 200 |<br /> | +-----------------------------------------------------+<br /> $FFFAA3|byte |Timer C Data |R/W (TT)<br /> $FFFAA5|byte |Timer D Data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFAA7|byte |Sync Character |R/W (TT)<br /> $FFFAA9|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W (TT)<br /> | |Clock divide (1 - div by 16) ---------' | | | | | | ||<br /> | |Word Length 00 - 8 bits ----------------+-+ | | | | ||<br /> | | 01 - 7 bits ----------------+-+ | | | | ||<br /> | | 10 - 6 bits ----------------+-+ | | | | ||<br /> | | 11 - 5 bits ----------------+-' | | | | ||<br /> | |Bits Stop Start Format | | | | ||<br /> | |00 0 0 Synchronous ----------------+-+ | | ||<br /> | |01 1 1 Asynchronous ---------------+-+ | | ||<br /> | |10 1 1.5 Asynchronous ---------------+-+ | | ||<br /> | |11 1 2 Asynchronous ---------------+-' | | ||<br /> | |Parity (0 - ignore parity bit) -----------------' | ||<br /> | |Parity (0 - odd parity,1 - even) -----------------' ||<br /> | |Unused ---------------------------------------------'|<br /> $FFFAAB|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |Buffer full --------------------------' | | | | | | ||<br /> | |Overrun error --------------------------' | | | | | ||<br /> | |Parity error -----------------------------' | | | | ||<br /> | |Frame error --------------------------------' | | | ||<br /> | |Found - Search/Break detected ----------------' | | ||<br /> | |Match/Character in progress --------------------' | ||<br /> | |Synchronous strip enable -------------------------' ||<br /> | |Receiver enable bit --------------------------------'|<br /> $FFFAAD|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |Buffer empty -------------------------' | | | | | | ||<br /> | |Underrun error -------------------------' | | | | | ||<br /> | |Auto turnaround --------------------------' | | | | ||<br /> | |End of transmission ------------------------' | | | ||<br /> | |Break ----------------------------------------' | | ||<br /> | |High bit ---------------------------------------' | ||<br /> | |Low bit ------------------------------------------' ||<br /> | |Transmitter enable ---------------------------------'|<br /> $FFFAAF|byte |USART data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############6850 ACIA I/O Chips ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFC00|byte |Keyboard ACIA control BIT 7 6 5 4 3 2 1 0|W<br /> | |Rx Int enable (1 - enable) -----------' | | | | | | ||<br /> | |Tx Interrupts | | | | | | ||<br /> | |00 - RTS low, Tx int disable -----------+-+ | | | | ||<br /> | |01 - RTS low, Tx int enable ------------+-+ | | | | ||<br /> | |10 - RTS high, Tx int disable ----------+-+ | | | | ||<br /> | |11 - RTS low, Tx int disable, | | | | | | ||<br /> | | Tx a break onto data out ----------+-' | | | | ||<br /> | |Settings | | | | ||<br /> | |000 - 7 bit, even, 2 stop bit --------------+-+-+ | ||<br /> | |001 - 7 bit, odd, 2 stop bit ---------------+-+-+ | ||<br /> | |010 - 7 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |011 - 7 bit, odd, 1 stop bit ---------------+-+-+ | ||<br /> | |100 - 8 bit, 2 stop bit --------------------+-+-+ | ||<br /> | |101 - 8 bit, 1 stop bit --------------------+-+-+ | ||<br /> | |110 - 8 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |111 - 8 bit, odd, 1 stop bit ---------------+-+-' | ||<br /> | |Clock divide | ||<br /> | |00 - Normal --------------------------------------+-+|<br /> | |01 - Div by 16 -----------------------------------+-+|<br /> | |10 - Div by 64 -----------------------------------+-+|<br /> | |11 - Master reset --------------------------------+-'|<br /> $FFFC00|byte |Keyboard ACIA control BIT 7 6 5 4 3 2 1 0|R<br /> | |Interrupt request --------------------' | | | | | | ||<br /> | |Parity error ---------------------------' | | | | | ||<br /> | |Rx overrun -------------------------------' | | | | ||<br /> | |Framing error ------------------------------' | | | ||<br /> | |CTS ------------------------------------------' | | ||<br /> | |DCD --------------------------------------------' | ||<br /> | |Tx data register empty ---------------------------' ||<br /> | |Rx data register full ------------------------------'|<br /> $FFFC02|byte |Keyboard ACIA data |R/W<br /> $FFFC04|byte |MIDI ACIA control BIT 7 6 5 4 3 2 1 0|W<br /> | |Rx Int enable (1 - enable) -----------' | | | | | | ||<br /> | |Tx Interrupts | | | | | | ||<br /> | |00 - RTS low, Tx int disable -----------+-+ | | | | ||<br /> | |01 - RTS low, Tx int enable ------------+-+ | | | | ||<br /> | |10 - RTS high, Tx int disable ----------+-+ | | | | ||<br /> | |11 - RTS low, Tx int disable, | | | | | | ||<br /> | | Tx a break onto data out ----------+-' | | | | ||<br /> | |Settings | | | | ||<br /> | |000 - 7 bit, even, 2 stop bit --------------+-+-+ | ||<br /> | |001 - 7 bit, odd, 2 stop bit ---------------+-+-+ | ||<br /> | |010 - 7 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |011 - 7 bit, odd, 1 stop bit ---------------+-+-+ | ||<br /> | |100 - 8 bit, 2 stop bit --------------------+-+-+ | ||<br /> | |101 - 8 bit, 1 stop bit --------------------+-+-+ | ||<br /> | |110 - 8 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |111 - 8 bit, odd, 1 stop bit ---------------+-+-' | ||<br /> | |Clock divide | ||<br /> | |00 - Normal --------------------------------------+-+|<br /> | |01 - Div by 16 -----------------------------------+-+|<br /> | |10 - Div by 64 -----------------------------------+-+|<br /> | |11 - Master reset --------------------------------+-'|<br /> $FFFC04|byte |MIDI ACIA control BIT 7 6 5 4 3 2 1 0|R<br /> | |Interrupt request --------------------' | | | | | | ||<br /> | |Parity error ---------------------------' | | | | | ||<br /> | |Rx overrun -------------------------------' | | | | ||<br /> | |Framing error ------------------------------' | | | ||<br /> | |CTS ------------------------------------------' | | ||<br /> | |DCD --------------------------------------------' | ||<br /> | |Tx data register empty ---------------------------' ||<br /> | |Rx data register full ------------------------------'|<br /> $FFFC06|byte |MIDI ACIA data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Realtime Clock ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFC21|byte |S_Units |???<br /> $FFFC23|byte |S_Tens |???<br /> $FFFC25|byte |M_Units |???<br /> $FFFC27|byte |M_Tens |???<br /> $FFFC29|byte |H_Units |???<br /> $FFFC2B|byte |H_Tens |???<br /> $FFFC2D|byte |Weekday |???<br /> $FFFC2F|byte |Day_Units |???<br /> $FFFC31|byte |Day_Tens |???<br /> $FFFC33|byte |Mon_Units |???<br /> $FFFC35|byte |Mon_Tens |???<br /> $FFFC37|byte |Yr_Units |???<br /> $FFFC39|byte |Yr_Tens |???<br /> $FFFC3B|byte |Cl_Mod |???<br /> $FFFC3D|byte |Cl_Test |???<br /> $FFFC3F|byte |Cl_Reset |???<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############ROM ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FA0000| | |<br /> : | |128K ROM expansion cartridge port |R<br /> $FBFFFF| | |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FC0000| | |<br /> : | |192K System ROM |R<br /> $FEFFFF| | |<br /> -------+-----+-----------------------------------------------------+----------<br /> <br /> Atari 32 bit Memory Map<br /> <br /> Addresses Description<br /> -------------------+----------------------------------------------------------<br /> $00000000-$00DFFFFF|ST RAM<br /> $00E00000-$00EFFFFF|512k TOS ROMs<br /> $00F00000-$00F9FFFF|Reserved I/O Space<br /> $00FA0000-$00FBFFFF|128k ROM cartridge expansion port<br /> $00FC0000-$00FEFFFF|192k System ROM<br /> $00FF0000-$00FF7FFF|Reserved I/O Space<br /> $00FF8000-$00FFFFFF|ST/TT I/O<br /> $01000000-$013FFFFF|TT Fast Ram<br /> $01400000-$FDFFFFFF|Reserved<br /> $FE000000-$FEFFFFFF|VME A24/D16<br /> $FEFF0000-$FEFFFFFF|VME A16/D16<br /> $FF000000-$FFFFFFFF|ST 24 bit compatible shadow<br /> $FFD000xx-$FFD000xx|Set FastRAM refresh rate and generate a bus error<br /> -------------------+----------------------------------------------------------<br /> <br /> Cookie Jar<br /> Atari &quot;Official&quot; Cookies<br /> Cookie Description<br /> -------+----------------------------------------------------------------------<br /> _CPU | CPU Type Bit 7 6 5 4 3 2 1 0<br /> | Processor type is represented in decimal in the lowest byte.<br /> | (0 - 68000, 40 - 68040)<br /> -------+----------------------------------------------------------------------<br /> _VDO | Video Type BIT 17 16<br /> | Shifter Type | |<br /> | 00 - ST ---------------------------------------------------------+--+<br /> | 01 - STe --------------------------------------------------------+--+<br /> | 10 - TT ---------------------------------------------------------+--+<br /> | 11 - Falcon030 --------------------------------------------------+--'<br /> -------+----------------------------------------------------------------------<br /> _FDC | Floppy Drive Controller BIT 25 24 . 23-0<br /> | Floppy Format | | |<br /> | 00 - DD (Normal floppy interface) ------------------------+--+ |<br /> | 01 - HD (1.44 MB with 3.5&quot;) ------------------------------+--+ |<br /> | 10 - ED (2.88 MB with 3.5&quot;) ------------------------------+--' |<br /> | Controller ID |<br /> | 0 - No information available |<br /> | 'ATC' - Fully compatible interface built in a way that -------------+<br /> | behaves like part of the system. |<br /> | 'DP1' - &quot;DreamPark Development&quot;, all ID's beginning with -----------'<br /> | &quot;DP&quot; are reserved for Dreampark.<br /> -------+----------------------------------------------------------------------<br /> _FLK | File Locking<br /> | If present, GEMDOS supports file locking. Value represents version<br /> | number of the expansion.<br /> -------+----------------------------------------------------------------------<br /> _NET | Network Type<br /> | If present, there is GEMDOS network support. Points to 2 longs:<br /> | The first is the ID of the producer, and the second is the version<br /> | number.<br /> -------+----------------------------------------------------------------------<br /> _SLM | SLM Driver<br /> | Diablo-driver for the SLM laser printer. Value points to a<br /> | non-documented structure.<br /> -------+----------------------------------------------------------------------<br /> _INF | .INF Patch<br /> | When present, STEFIX (patch program for TOS 1.06) is active.<br /> -------+----------------------------------------------------------------------<br /> _SND | Sound Hardware BIT 5 4 3 2 1 0<br /> | CodeC (??) -----------------------------------------------' | | | | |<br /> | Connection Matrix ------------------------------------------' | | | |<br /> | DSP56001 -----------------------------------------------------' | | |<br /> | 16 Bit DMA Sound -----------------------------------------------' | |<br /> | 8 Bit DMA Sound --------------------------------------------------' |<br /> | YM2149 -------------------------------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> _MCH | Machine Type BIT 17 16<br /> | 00 - ST/Mega ST -------------------------------------------------+--+<br /> | 01 - STe &amp; Compatible Machines (See Below) ----------------------+--+<br /> | 10 - TT ---------------------------------------------------------+--+<br /> | 11 - Falcon030 --------------------------------------------------+--'<br /> | STe &amp; Compatible Machines BIT 5 4 3 2 1 0<br /> | 00000 - STe ----------------------------------------------+-+-+-+-+-+<br /> | 00001 - ST Book ------------------------------------------+-+-+-+-+-+<br /> | 10000 - Mega STe -----------------------------------------+-+-+-+-+-'<br /> -------+----------------------------------------------------------------------<br /> _SWI | Configuration Switches<br /> | State of configuration switches (MSTe/TT only)<br /> -------+----------------------------------------------------------------------<br /> _FRB | Fast Ram Buffer<br /> | (TT specific) 64k buffer for ACSI DMA<br /> | 0 - no buffers assigned Not 0 - address of FastRam buffer<br /> -------+----------------------------------------------------------------------<br /> _FPU | FPU Type<br /> | Software FPU BIT 3 2 1 0<br /> | 68040's internal FPU -----------------------------------------' | | |<br /> | 01 - 6888x present ---------------------------------------------+-+ |<br /> | 10 - 68881 for sure --------------------------------------------+-+ |<br /> | 11 - 68882 for sure --------------------------------------------+-' |<br /> | SFP004 present -----------------------------------------------------'<br /> | Hardware FPU BIT 11 10 9 8<br /> | 68040's internal FPU ----------------------------------------' | | |<br /> | 01 - 6888x present ---------------------------------------------+-+ |<br /> | 10 - 68881 for sure --------------------------------------------+-+ |<br /> | 11 - 68882 for sure --------------------------------------------+-' |<br /> | SFP004 present -----------------------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> _OOL | PoolFix<br /> | Value corresponds to PoolFix version<br /> -------+----------------------------------------------------------------------<br /> _AKP | Keyboard/Language Configuration<br /> | Keyboard Configuration Bit 15-8<br /> | 1 - German 5 - Italian -------------------------------------------+<br /> | 2 - French 7 - Swiss French --------------------------------------+<br /> | 4 - Spanish 8 - Swiss German --------------------------------------+<br /> | All others - English -----------------------------------------------'<br /> | Language Configuration BIT 7-0<br /> | 1 - German 5 - Italian -------------------------------------------+<br /> | 2 - French 7 - Swiss French --------------------------------------+<br /> | 4 - Spanish 8 - Swiss German --------------------------------------+<br /> | All others - English -----------------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> _IDT | International Date/Time Format<br /> | Time Format BIT 12<br /> | 0 - AM/PM, 1 - 24 hours --------------------------------------------+<br /> | Date Format BIT 9 8<br /> | 00 - MMDDYY ------------------------------------------------------+-+<br /> | 01 - DDMMYY ------------------------------------------------------+-+<br /> | 10 - YYMMDD ------------------------------------------------------+-+<br /> | 11 - YYDDMM ------------------------------------------------------+-'<br /> | Separator for date BIT 7-0<br /> | ASCII Value (i.e. &quot;.&quot; or &quot;/&quot;) --------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> MiNT | MiNT<br /> | Present if MiNT/MultiTOS is active. Value represents the version<br /> | number of the MiNT kernel in hex (0x104 = 1.04)<br /> -------+----------------------------------------------------------------------<br /> &lt;/pre&gt;<br /> <br /> [[Category:Programming]]<br /> [[Category:Memory Address]]</div>

Cyprian https://www.temlib.org/AtariForumWiki/index.php?title=Atari_ST/STe/MSTe/TT/F030_Hardware_Register_Listing&diff=22857 2023-09-13T13:55:34Z

<p>Cyprian: $FF8205/07/09 R/W on STe</p> <hr /> <div>Based on:<br /> * https://temlib.org/AtariForumWiki/index.php/Atari_ST/STe/MSTe/TT/F030_Hardware_Register_Listing<br /> * https://github.com/Number0000009/atari-wiki/blob/master/Atari%20ST%20STe%20MSTe%20TT%20F030%20Hardware%20Register%20Listing.txt<br /> * https://mikro.naprvyraz.sk/docs/Memory%20Maps/FALREG.TXT<br /> * https://mikro.naprvyraz.sk/docs/mikro/videl.html<br /> * http://cd.textfiles.com/atarilibrary/atari_cd10/DISKS/AC10DISK/ATOZBOOK/M.TXT<br /> <br /> &lt;pre&gt;<br /> .---------------------------------------------------.<br /> |Atari ST/STe/MSTe/TT/F030 Hardware Register Listing|<br /> `---------------------------------------------------'<br /> <br /> <br /> <br /> Address Description Space<br /> -------+----------------------------------------------------------------+-----<br /> ########CPU Reset Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $000000|Reset : Initial SSP |SP<br /> $000004|Reset : Initial PC |SP<br /> -------+----------------------------------------------------------------+-----<br /> ########CPU Exception Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $000008|Bus Error |SD<br /> $00000C|Address Error |SD<br /> $000010|Illegal Instruction |SD<br /> $000014|Zero Divide |SD<br /> $000018|CHK, CHK2 Instruction |SD<br /> $00001C|cpTRAPcc, TRAPcc, TRAPV |SD<br /> $000020|Privilege Violation |SD<br /> $000024|Trace |SD<br /> $000028|Line 1010 Emulator (LineA) |SD<br /> $00002C|Line 1111 Emulator (LineF) |SD<br /> $000030|(Unassigned, Reserved) |SD<br /> $000034|Coprocessor Protocol Violation (68030) |SD<br /> $000038|Format Error (68010) |SD<br /> $00003C|Uninitialized Interrupt Vector |SD<br /> $000040|(Unassigned, Reserved) |SD<br /> : | : : | :<br /> $00005F|(Unassigned, Reserved) |SD<br /> $000060|Spurious Interrupt (Bus error during interrupt) |SD <br /> -------+----------------------------------------------------------------+-----<br /> ########Auto-Vector Interrupts ######<br /> -------+----------------------------------------------------------------+-----<br /> $000064|Level 1 Int Autovector (TT VME) |SD<br /> $000068|Level 2 Int Autovector (HBL) |SD<br /> $00006C|Level 3 Int Autovector (TT VME) |SD<br /> $000070|Level 4 Int Autovector (VBL) |SD<br /> $000074|Level 5 Int Autovector |SD<br /> $000078|Level 6 Int Autovector (MFP) |SD<br /> $00007C|Level 7 Int Autovector |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########Trap Instruction Vectors (Trap #n = Vector number + 32 + n) ######<br /> -------+----------------------------------------------------------------+-----<br /> $000080|Trap #0 |SD<br /> $000084|Trap #1 (GemDOS) |SD<br /> $000088|Trap #2 (AES/VDI) |SD<br /> $00008C|Trap #3 |SD<br /> $000090|Trap #4 |SD<br /> $000094|Trap #5 |SD<br /> $000098|Trap #6 |SD<br /> $00009C|Trap #7 |SD<br /> $0000A0|Trap #8 |SD<br /> $0000A4|Trap #9 |SD<br /> $0000A8|Trap #10 |SD<br /> $0000AC|Trap #11 |SD<br /> $0000B0|Trap #12 |<br /> $0000B4|Trap #13 (BIOS) |SD<br /> $0000B8|Trap #14 (XBIOS) |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########Math Coprocessor Vectors (68881/68882/Internal) ######<br /> -------+----------------------------------------------------------------+-----<br /> $0000C0|FFCP Branch or Set on Unordered Condition |SD<br /> $0000C4|FFCP Inexact Result |SD<br /> $0000C8|FFCP Divide by Zero |SD<br /> $0000CC|FFCP Underflow |SD<br /> $0000D0|FFCP Operand Error |SD<br /> $0000D4|FFCP Overflow |SD<br /> $0000D8|FFCP Signaling NAN |SD<br /> $0000DC|(Unassigned, Reserved) |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########PMMU Coprocessor Vectors (68851/Internal) ######<br /> -------+----------------------------------------------------------------+-----<br /> $0000E0|MMU Configuration Error |SD<br /> $0000E4|MC68851, not used by MC68030 |SD<br /> $0000E8|MC68851, not used by MC68030 |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########Miscellaneous Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $0000EC|(Unassigned, Reserved) |SD<br /> : | : : | :<br /> $0000FF|(Unassigned, Reserved) |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########User Assigned Interrupt Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $000100|ST-MFP-0 - Centronics busy |SD<br /> $000104|ST-MFP-1 - RS-232 DCD |SD<br /> $000108|ST-MFP-2 - RS-232 CTS |SD<br /> $00010C|ST-MFP-3 - Blitter done |SD<br /> $000110|ST-MFP-4 - Timer D (USART timer) |SD<br /> $000114|ST-MFP-5 - Timer C (200hz Clock) |SD<br /> $000118|ST-MFP-6 - Keyboard/MIDI (ACIA) |SD<br /> $00011C|ST-MFP-7 - FDC/HDC |SD<br /> $000120|ST-MFP-8 - Timer B (HBL) |SD<br /> $000124|ST-MFP-9 - Send Error |SD<br /> $000128|ST-MFP-10 - Send buffer empty |SD<br /> $00012C|ST-MFP-11 - Receive error |SD<br /> $000130|ST-MFP-12 - Receive buffer full |SD<br /> $000134|ST-MFP-13 - Timer A (STe sound) |SD<br /> $000138|ST-MFP-14 - RS-232 Ring detect |SD<br /> $00013C|ST-MFP-15 - GPI7 - Monochrome Detect |SD<br /> $000140|TT-MFP-0 - GPI 0 |SD<br /> $000144|TT-MFP-1 - GPI 1 |SD<br /> $000148|TT-MFP-2 - SCC-DMA Controller |SD<br /> $00014C|TT-MFP-3 - Ring Indicator SCC B |SD<br /> $000150|TT-MFP-4 - Timer D |SD<br /> $000154|TT-MFP-5 - Timer C |SD<br /> $000158|TT-MFP-6 - (Reserved) GPI 4 |SD<br /> $00015C|TT-MFP-7 - SCSI DMA Controller |SD<br /> $000160|TT-MFP-8 - Timer B |SD<br /> $000164|TT-MFP-9 - Send Error |SD<br /> $000168|TT-MFP-10 - Send buffer empty |SD<br /> $00016C|TT-MFP-11 - Receive error |SD<br /> $000170|TT-MFP-12 - Receive buffer full |SD<br /> $000174|TT-MFP-13 - Timer A |SD<br /> $000176|TT-MFP-14 - TT Clock (MC146818A) |SD<br /> $00017C|TT-MFP-15 - TT-SCSI Drive Controller NCR 5380 |SD<br /> $000180|SCC Interrupt |SD<br /> $0001BC|SCC Interrupt |SD<br /> $0001C0|User Defined, Unused |SD<br /> : | : : : | :<br /> $0003FC|User Defined, Unused |SD<br /> -------+----------------------------------------------------------------+-----<br /> <br /> Address Size Description Name<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############System Crash Page ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $000380|long |Validates System Crash Page if $12345678 |proc_lives<br /> $000384|.....|Saved registers D0-D7 |proc_dregs<br /> $0003A4|.....|Saved registers A0-A7 |proc_aregs<br /> $0003C4|long |Vector number of crash exception |proc_enum<br /> $0003C8|long |Saved USP |proc_usp<br /> $0003CC|.....|Saved 16 words from exception stack |proc_stk<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############System Variables ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $000400|long |GEM Event timer vector |etv_timer<br /> $000404|long |GEM Critical error handler |etv_critic<br /> $000408|long |GEM Program termination vector |etv_term<br /> $00040C|long |GEM Additional vector #1 (Unused) |etv_xtra<br /> : | : | : : : : : | :<br /> $00041C|long |GEM Additional vector #5 (Unused) |etv_xtra<br /> $000420|long |Validates memory configuration if $752019F3 |memvalid<br /> $000424|word |Copy of contents of $FF8001 |memctrl<br /> $000426|long |Validates resvector if $31415926 |resvalid<br /> $00042A|long |Reset vector |resvector<br /> $00042E|long |Physical top of RAM |phystop<br /> $000432|long |Start of TPA (user memory) |_membot<br /> $000436|long |End of TPA (user memory) |_memtop<br /> $00043A|long |Validates memcntrl and memconf if $237698AA |memval2<br /> $00043E|word |If nonzero, floppy disk VBL routine is disabled |flock<br /> $000440|word |Floppy Seek rate - 0:6ms, 1:12ms, 2:2ms, 3:3ms |seekrate<br /> $000442|word |Time between two timer calls (in milliseconds) |_timer_ms<br /> $000444|word |If not zero, verify floppy disk writes |_fverify<br /> $000446|word |Default boot device |_bootdev<br /> $000448|word |0 - NTSC (60hz), &lt;&gt;0 - PAL (50hz) |palmode<br /> $00044A|word |Default video resolution |defshiftmod<br /> $00044C|word |Copy of contents of $FF8260 |sshiftmod<br /> $00044E|long |Pointer to video RAM (logical screen base) |_v_bas_ad<br /> $000452|word |If not zero, VBL routine is not executed |vblsem<br /> $000454|word |Number of vertical blank routines |nvbls<br /> $000456|long |Pointer to list of vertical blank routines |_vblqueue<br /> $00045A|long |If not zero, points to color palette to be loaded |colorptr<br /> $00045E|long |If not zero, points to video ram for next VBL |screenpt<br /> $000462|long |Counter for number of VBLs |_vbclock<br /> $000466|long |Number of VBL routines executed |_frclock<br /> $00046A|long |Vector for hard disk initialization |hdv_init<br /> $00046E|long |Vector for resolution change |swv_vec<br /> $000472|long |Vector for getbpb for hard disk |hdv_bpb<br /> $000476|long |Vector for read/write routine for hard disk |hdv_rw<br /> $00047A|long |Vector for hard disk boot |hdv_boot<br /> $00047E|long |Vector for hard disk media change |hdv_mediach<br /> $000482|word |If not zero, attempt to load &quot;COMMAND.PRG&quot; on boot |_comload<br /> $000484|byte |Attribute vector for console output BIT 3 2 1 0|conterm<br /> | |Return &quot;kbshift&quot; for BIOS conin --------------' | | ||<br /> | |System bell (1 - on) ---------------------------' | ||<br /> | |Key repeat (1 - on) ------------------------------' ||<br /> | |Key click (1 - on) ---------------------------------'|<br /> $000486|long |Return address for TRAP #14 (unused)|trp14ret<br /> $00048A|long |Return address for critical error handler (unused)|criticret<br /> $00048E|long |Memory descriptor block |themd<br /> $00049E|long |Space for additional memory descriptors |themdmd<br /> $0004A2|long |Pointer to BIOS save registers block |savptr<br /> $0004A6|word |Number of connected floppy drives |_nflops<br /> $0004A8|long |Vector for screen output |con_state<br /> $0004AC|word |Temporary storage for cursor line position |save_row<br /> $0004AE|long |Pointer to save area for exception processing |sav_context<br /> $0004B2|long |Pointer to buffer control block for GEMDOS data |_bufl<br /> $0004B6|long |Pointer to buffer control block for GEMDOS fat/dir |_bufl<br /> $0004BA|long |Counter for 200hz system clock |_hz_200<br /> $0004BC|long |Pointer to default environment string |the_env<br /> $0004C2|long |Bit allocation for physical drives (bit 0=A, 1=B..) |_drvbits<br /> $0004C6|long |Pointer to 1024-byte disk buffer |_dskbufp<br /> $0004CA|long |Pointer to autoexecute path |_autopath<br /> $0004CE|long |Pointer to VBL routine #1 |_vbl_lis<br /> : | : | : : : : : | :<br /> $0004EA|long |Pointer to VBL routine #8 |_vbl_lis<br /> $0004EE|word |Flag for screen -&gt; printer dump |_dumpflg<br /> $0004F0|word |Printer abort flag |_prtabt<br /> $0004F2|long |Pointer to start of OS |_sysbase<br /> $0004F6|long |Global shell pointer |_shell_p<br /> $0004FA|long |Pointer to end of OS |end_os<br /> $0004FE|long |Pointer to entry point of OS |exec_os<br /> $000502|long |Pointer to screen dump routine |scr_dump<br /> $000506|long |Pointer to _lstostat() |prv_lsto<br /> $00050A|long |Pointer to _lstout() |prv_lst<br /> $00050E|long |Pointer to _auxostat() |prv_auxo<br /> $000512|long |Pointer to _auxout() |prv_aux<br /> $000516|long |If AHDI, pointer to pun_info |pun_ptr<br /> $00051A|long |If $5555AAAA, reset |memval3<br /> $00051E|long |8 Pointers to input-status routines |xconstat<br /> $00053E|long |8 Pointers to input routines |xconin<br /> $00055E|long |8 Pointers to output-status routines |xcostat<br /> $00057E|long |8 Pointers to output routines |xconout<br /> $00059E|word |If not 0, then not 68000 - use long stack frames |_longframe<br /> $0005A0|long |Pointer to cookie jar |_p_cookies<br /> $0005A4|long |Pointer to end of FastRam |ramtop<br /> $0005A8|long |Validates ramtop if $1357BD13 |ramvalid<br /> $0005AC|long |Pointer to routine for system bell |bell_hook<br /> $0005B0|long |Pointer to routine for system keyclick |kcl_hook<br /> -------+-----+-----------------------------------------------------+----------<br /> <br /> Address Size Description Bits used Read/Write<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############OS ROMs ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $E00000|byte |TOS 512k ROMs |R<br /> : | : | : : : |:<br /> $EFFFFF|byte |TOS 512k ROMs |R<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############ADSPEED Configuration registers ########### <br /> -------+-----+-----------------------------------------------------+----------<br /> $F00000|byte |Switch to 16 Mhz |W<br /> $F10000|byte |Switch to 8 Mhz |W<br /> $F20000|byte |Turn on high speed ROM option in 16 Mhz |W<br /> $F30000|byte |Turn off high speed ROM option |W<br /> $F40000|byte |Unknown |W<br /> $F50000|byte |Turn off cache while in 16 Mhz |W<br /> | | &gt;&gt; Write 0 to an address to set it. &lt;&lt; |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############IDE Controller (Falcon, ST-Book, IDE cards) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $F00000|word |Data Register |R/W<br /> | | BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0|<br /> $F00002|word |Data Register |R/W<br /> | | BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0|<br /> $F00005|byte |Error Register BIT 7 6 5 4 3 2 1 0|R<br /> | |Bad block mark -----------------------' | | | | | | ||<br /> | |Uncorrectable error --------------------' | | | | | ||<br /> | |Media change -----------------------------' | | | | ||<br /> | |ID-Field not found -------------------------' | | | ||<br /> | |Media change requested -----------------------' | | ||<br /> | |Command aborted --------------------------------' | ||<br /> | |Track 0 not found --------------------------------' ||<br /> | |DAM not found --------------------------------------'|<br /> $F00005|byte |Write Precompensation |W<br /> $F00009|byte |Sector Count Register |W<br /> $F0000D|byte |Sector Number Register |W<br /> $F00011|byte |Cylinder Low Register BIT 7 6 5 4 3 2 1 0|W<br /> $F00015|byte |Cylinder High Register BIT 1 0|W<br /> $F00019|byte |Drive Head Register BIT 7 6 5 4 3 2 1 0|W<br /> | |Sector size (512 bytes, fixed) -------+ + + | | | | ||<br /> | |Drive (0 - Master, 1 - Slave) --------------' | | | ||<br /> | |Head number ----------------------------------+ + + +|<br /> $F0001D|byte |Status Register BIT 7 6 5 4 3 2 1 0|R<br /> | |Drive busy with executing Command ----' | | | | | | ||<br /> | |Drive Ready ----------------------------' | | | | | ||<br /> | |Drive Write Fault ------------------------' | | | | ||<br /> | |Drive Seek Complete ------------------------' | | | ||<br /> | |Data Request ---------------------------------' | | ||<br /> | |Corrected Data ---------------------------------' | ||<br /> | |Index pulse --------------------------------------' ||<br /> | |Error ----------------------------------------------'|<br /> $F0001D|byte |Command Register |W<br /> $F00039|byte |Alternate Status Register |R<br /> | |2nd status register, like 1st no deletion of the IRQ | |<br /> $F00039|byte |Data Output Register BIT 2 1 .|W<br /> | |Software Reset (1 - on)-------------------------+ | |<br /> | |Interrupt after end of Command (0 - on) ----------+ |<br /> $F0003D|byte |Active address BIT 6 5 4 3 2 1 0|R<br /> | |Drive is writing (0 - on) --------------' | | | | | ||<br /> | |Negated number of head number ------------+ + + + | ||<br /> | |Slave Drive Select (0 - on) ----------------------' ||<br /> | |Master Drive Select (0 - on) -----------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############OS ROMs ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FC0000|byte |TOS 192k ROMs |R<br /> : | : | : : : |:<br /> $FEFFFF|byte |TOS 192k ROMs |R<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############ST MMU Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8001|byte |MMU memory configuration BIT 3 2 1 0|R/W<br /> | |Bank 0 | | | ||<br /> | |00 - 128k ------------------------------------+-+ | ||<br /> | |01 - 512k ------------------------------------+-+ | ||<br /> | |10 - 2m --------------------------------------+-+ | ||<br /> | |11 - reserved --------------------------------+-' | ||<br /> | |Bank 1 | ||<br /> | |00 - 128k ----------------------------------------+-+|<br /> | |01 - 512k ----------------------------------------+-+|<br /> | |10 - 2m ------------------------------------------+-+|<br /> | |11 - reserved ------------------------------------+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon030 Processor Control ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8007|byte |Falcon Bus Control BIT 6 5 . 3 2 . 0|R/W (F030)<br /> | |RESET behavior -------------------------+ | | | ||<br /> | | 0 = always cold start ----------------+ | | | ||<br /> | | 1 = normal, &quot;memvalid&quot; is observed ---+ | | | ||<br /> | |STe Bus Emulation ------------------------' | | ||<br /> | | 0 = STE --------------------------------' | | ||<br /> | | 1 = Falcon -----------------------------' | | ||<br /> | |Blitter flag ---------------------------------' | ||<br /> | | 0 = BLiTTER On -----------------------------' | ||<br /> | | 1 = BLiTTER Off ----------------------------' | ||<br /> | |Blitter clock-----------------------------------' ||<br /> | | 0 - 8mhz, ------------------------------------' ||<br /> | | 1 - 16mhz ------------------------------------' ||<br /> | |68030 clock ----------------------------------------'|<br /> | | 0 - 8mhz -----------------------------------------'|<br /> | | 1 - 16mhz ----------------------------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############SHIFTER Video Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8201|byte |Video screen memory position (High byte) |R/W<br /> $FF8203|byte |Video screen memory position (Mid byte) |R/W<br /> $FF820D|byte |Video screen memory position (Low byte) |R/W (STe)<br /> $FF8205|byte |Video address pointer (High byte) |R (R/W STe)<br /> $FF8207|byte |Video address pointer (Mid byte) |R (R/W STe)<br /> $FF8209|byte |Video address pointer (Low byte) |R (R/W STe)<br /> $FF820E|word |Offset to next line |R/W (F030)<br /> $FF820F|byte |Width of a scanline (width in words-1) |R/W (STe)<br /> $FF8210|word |Width of a scanline (width in words) |R/W (F030)<br /> $FF8264|byte |Horizontal scroll register without prefetch (0-15) |R/W (STe)<br /> $FF8265|byte |Horizontal scroll register with prefetch (0-15) |R/W (STe)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF820A|byte |Video synchronization mode BIT 1 0|R/W<br /> | |0 - 60hz, 1 - 50hz -------------------------------+ ||<br /> | |0 - internal, 1 - external sync ------------------' || (TT)<br /> | |0 - internal, 1 - external sync --------------------'| (!TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> | | BIT 11111198 76543210|<br /> | | 543210 |<br /> | | ST color value .....RRr .GGr.BBb|<br /> | | STe color value ....rRRR gGGGbBBB|<br /> $FF8240|word |Video palette register 0 Lowercase = LSB|R/W<br /> : | : | : : : : | :<br /> $FF825E|word |Video palette register 15 |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8260|byte |Shifter resolution BIT 1 0|R/W<br /> | |00 320x200x4 bitplanes (16 colors) ---------------+-+|<br /> | |01 640x200x2 bitplanes (4 colors) ----------------+-+|<br /> | |10 640x400x1 bitplane (1 colors) ----------------+-'|<br /> $FF8262|word |TT Shifter resolution BIT 15 . . 12|R/W (TT)<br /> | |Sample/Hold mode ----------------------------' ||<br /> | |Hypermono mode -------------------------------------'|<br /> | |Video Mode BIT 10 9 8|<br /> | |000 320x200x4 bitplanes (16 colors) -----------+-+-+|<br /> | |001 640x200x2 bitplanes (4 colors) ------------+-+-+|<br /> | |010 640x400x1 bitplane (2 colors)(Duochrome) -+-+-+|<br /> | |100 640x480x4 bitplanes (16 colors) -----------+-+-+|<br /> | |110 1280x960x1 bitplane (2 colors) ------------+-+-+|<br /> | |111 320x480x8 bitplanes (256 colors) ----------+-+-'|<br /> | |ST Palette Bank BIT 3 2 1 0|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF827E|word |STACY Display Driver BIT 10 9|R/W(STACY)<br /> | |Backlight on/off ---------------------------------+ ||<br /> | |Display on/off -------------------------------------+| <br /> -------+-----+-----------------------------------------------------+----------<br /> | | BIT 11111198 76543210|<br /> | | 543210 |<br /> | | TT color value ....RRRr GGGgBBBb|<br /> $FF8400|word |TT Palette 0 Lowercase = LSB|R/W (TT)<br /> : | : | : : : | : :<br /> $FF85FE|word |TT Palette 255 |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon030 VIDEL Video Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8006|byte |Monitor Type BIT 7 6 5 4 3 2 1 0|R (F030)<br /> | |Monitor Type (M0,M1) -----------------+-+ | | | | | ||<br /> | |00 - Monochrome (SM124) --------------+-+ | | | | | ||<br /> | |01 - RGB (SC1224) --------------------+-+ | | | | | ||<br /> | |10 - VGA Color -----------------------+-+ | | | | | ||<br /> | |11 - Television ----------------------+-+ | | | | | ||<br /> | |ST-RAM size ------------------------------+-+ | | | ||<br /> | | 00 = 1MB -------------------------------+-+ | | | ||<br /> | | 01 = 4MB -------------------------------+-+ | | | ||<br /> | | 10 = 16MB ------------------------------+-+ | | | ||<br /> | |ROM Wait Status ------------------------------+ + | ||<br /> | | 00 = Reserved ------------------------------+ + | ||<br /> | | 01 = 2 Wait (default) ----------------------+ + | ||<br /> | | 10 = 1 Wait --------------------------------+ + | ||<br /> | | 11 = 0 Wait --------------------------------+ + | ||<br /> | |Video bus width ----------------------------------+ ||<br /> | | 0 = 16 Bit, -----------------------------------+ ||<br /> | | 1 = 32 Bit (default) ---------------------------+ ||<br /> | |RAM Wait Status ------------------------------------+|<br /> | | 0 = 1 Wait (default) ----------------------------+|<br /> | | 1 = 0 Wait --------------------------------------+|<br /> $FF820E|word |Offset to next line |R/W (F030)<br /> $FF8210|word |VWRAP - Linewidth in words |R/W (F030)<br /> $FF8266|word |SPSHIFT BIT 10 9 8 . 6 5 4 3 2 1 0|R/W (F030)<br /> | |2-colour mode ------------------' | | | | | | | | ||<br /> | |Overlay mode ---------------------' | | | | | | | ||<br /> | |Truecolour mode --------------------' | | | | | | ||<br /> | |Use external Hsync (1 - on) ------------' | | | | | ||<br /> | |Use external Vsync (1 - on) --------------' | | | | ||<br /> | |8 Bitplane mode ----------------------------' | | | ||<br /> | |Color Palette Bank from 256 colors (0-15) ----+-+-+-+|<br /> | +-----------------------------------------------------+<br /> | | Horizontal Control Registers (BIT 9-0)|<br /> $FF8280|word |HHC - Horizontal Hold Counter |R (F030)<br /> $FF8282|word |HHT - Horizontal Hold Timer |R/W (F030)<br /> $FF8284|word |HBB - Horizontal Border Begin |R/W (F030)<br /> $FF8286|word |HBE - Horizontal Border End |R/W (F030)<br /> $FF8288|word |HDB - Horizontal Display Begin |R/W (F030)<br /> $FF828A|word |HDE - Horizontal Display End |R/W (F030)<br /> $FF828C|word |HSS - Horizontal SS |R/W (F030)<br /> $FF828E|word |HFS - Horizontal FS |R/W (F030)<br /> $FF8290|word |HEE - Horizontal EE |R/W (F030)<br /> | +-----------------------------------------------------+<br /> | | Vertical Control Registers (BIT 10-0)| <br /> $FF82A0|word |VFC - Vertcial Frequency Counter |R (F030)<br /> $FF82A2|word |VFT - Vertical Frequency Timer |R/W (F030)<br /> $FF82A4|word |VBB - Vertical Border Begin (count in 1/2 lines)|R/W (F030)<br /> $FF82A6|word |VBE - Vertical Border End (count in 1/2 lines)|R/W (F030)<br /> $FF82A8|word |VDB - Vertical Display Begin |R/W (F030)<br /> $FF82AA|word |VDE - Vertical Display End |R/W (F030)<br /> $FF82AC|word |VSS - Vertical SS |R/W (F030)<br /> | +-----------------------------------------------------+<br /> $FF82C0|word |Video Control (VCO) (Super78 puts $182 here) |R/W (F030)<br /> | | BIT 8 7 6 5 . 3 2 1 0|<br /> | |Hz base offset ---------------------' | | | | | | ||<br /> | | 0: 128 cycles --------------------' | | | | | | ||<br /> | | (ST Low/Mid on RGB | | | | | | ||<br /> | | and ST Hi on SM124) | | | | | | ||<br /> | | 1: 64 cycles (all the others) ---' | | | | | | ||<br /> | |Videobus width -----------------------' | | | | | ||<br /> | | 0: 16 Bit-Videobus -----------------' | | | | | ||<br /> | | 1: 32 Bit-Videobus (Falcon) --------' | | | | | ||<br /> | |HSync-Impulse --------------------------' | | | | ||<br /> | | 0: negative HSync-Impulse (5V &gt; 0V) --' | | | | ||<br /> | | 1: positive HSync-Impulse (0V &gt; 5V) --' | | | | ||<br /> | |VSync-Impulse ----------------------------' | | | ||<br /> | | 0: negative VSync-Impulse (5V &gt; 0V) ----' | | | ||<br /> | | 1: positive VSync-Impulse (0V &gt; 5V) ----' | | | ||<br /> | |Half-line-HSyncs------------------------------' | | ||<br /> | | 0: No Half-line-HSyncs ---------------------' | | ||<br /> | | 1: 15 Half-line-HSyncs from start of -------' | | ||<br /> | |Video base clock -------------------------------' | ||<br /> | | 0: Video base clock 32 MHz -------------------' | ||<br /> | | 1: Video base clock 25.175 MHz ---------------' | ||<br /> | |Monitor Type (M0,M1 same as bit 7&amp;6 in $FF0006) --+-+|<br /> | | 00 - Monochrome (SM124) ------------------------+-+|<br /> | | 01 - RGB (SC1224) ------------------------------+-+|<br /> | | 10 - VGA Color ---------------------------------+-+|<br /> | | 11 - Television --------------------------------+-+|<br /> $FF82C2|word |VCO - Video Control BIT 3 2 1 0|R/W (F030)<br /> | |Pixel width ----------------------------------+-+ | ||<br /> | | 00: 4 cycles/pixel -------------------------+-+ | ||<br /> | | 01: 2 cycles/pixel -------------------------+-+ | ||<br /> | | 10: 1 cycle/pixel -------------------------+-+ | ||<br /> | | 11: n/a -------------------------+-+ | ||<br /> | |Skip line (interlace) (1-on) ---------------------' ||<br /> | |Double lines (1-on) --------------------------------'| <br /> -------+-----+-----------------------------------------------------+----------<br /> ##############DMA/WD1772 Disk controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8600| |Reserved |<br /> $FF8602| |Reserved |<br /> $FF8604|word |FDC access/sector count |R/W<br /> $FF8606|word |DMA mode/status BIT 2 1 0|R<br /> | |Condition of FDC DATA REQUEST signal -----------' | ||<br /> | |0 - sector count null,1 - not null ---------------' ||<br /> | |0 - no error, 1 - DMA error ------------------------'|<br /> $FF8606|word |DMA mode/status BIT 8 7 6 . 4 3 2 1 .|W<br /> | |0 - read FDC/HDC,1 - write ---------' | | | | | | | |<br /> | |0 - HDC access,1 - FDC access --------' | | | | | | |<br /> | |0 - DMA on,1 - no DMA ------------------' | | | | | |<br /> | |Reserved ---------------------------------' | | | | |<br /> | |0 - FDC reg,1 - sector count reg -----------' | | | |<br /> | |0 - FDC access,1 - HDC access ----------------' | | |<br /> | |0 - pin A1 low, 1 - pin A1 high ----------------' | |<br /> | |0 - pin A0 low, 1 - pin A0 high ------------------' |<br /> $FF8609|byte |DMA base and counter (High byte) |R/W<br /> $FF860B|byte |DMA base and counter (Mid byte) |R/W<br /> $FF860D|byte |DMA base and counter (Low byte) |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############TT-SCSI DMA Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8701|byte |DMA Address Pointer (Highest byte) |R/W (TT)<br /> $FF8703|byte |DMA Address Pointer (High byte) |R/W (TT)<br /> $FF8705|byte |DMA Address Pointer (Low byte) |R/W (TT)<br /> $FF8707|byte |DMA Address Pointer (Lowest byte) |R/W (TT)<br /> $FF8709|byte |DMA Byte Count (Highest byte) |R/W (TT)<br /> $FF870B|byte |DMA Byte Count (High byte) |R/W (TT)<br /> $FF870D|byte |DMA Byte Count (Low byte) |R/W (TT)<br /> $FF870F|byte |DMA Byte Count (Lowest byte) |R/W (TT)<br /> $FF8710|word |Residue Data Register (High Word) |R (TT)<br /> $FF8712|word |Residue Data Register (Low Word) |R (TT)<br /> $FF8715|byte |Control register BIT 7 6 . . . . 1 0|R/W (TT)<br /> | |Bus error ----------------------------' | | ||<br /> | |Byte count zero ------------------------' | ||<br /> | |Enable -------------------------------------------' ||<br /> | |DMA Direction (1 - out to port) --------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############TT-SCSI Drive Controller NCR 5380 ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8781|byte |Data register |R/W (TT)<br /> $FF8783|byte |Init-Command Register |R/W (TT)<br /> $FF8785|byte |Mode Register |R/W (TT)<br /> $FF8787|byte |Target-Command Register |R/W (TT)<br /> $FF8789|byte |ID Select/SCSI Control Register |R/W (TT)<br /> $FF878B|byte |Status Register |R/W (TT)<br /> $FF878D|byte |Target Receive/Input Data |R/W (TT)<br /> $FF878F|byte |Initiate Receive/Reset |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############YM2149 Sound Chip ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8800|byte |Read data/Register select |R/W<br /> | |0 Channel A Freq Low BIT 7 6 5 4 3 2 1 0|<br /> | |1 Channel A Freq High BIT 3 2 1 0|<br /> | |2 Channel B Freq Low BIT 7 6 5 4 3 2 1 0|<br /> | |3 Channel B Freq High BIT 3 2 1 0|<br /> | |4 Channel C Freq Low BIT 7 6 5 4 3 2 1 0|<br /> | |5 Channel C Freq High BIT 3 2 1 0|<br /> | |6 Noise Freq BIT 5 4 3 2 1 0|<br /> | |7 Mixer Control BIT 7 6 5 4 3 2 1 0|<br /> | | Port B IN/OUT (1=Output) -----------' | | | | | | ||<br /> | | Port A IN/OUT ------------------------' | | | | | ||<br /> | | Channel C Noise (1=Off) ----------------' | | | | ||<br /> | | Channel B Noise --------------------------' | | | ||<br /> | | Channel A Noise ----------------------------' | | ||<br /> | | Channel C Tone (0=On) ------------------------' | ||<br /> | | Channel B Tone ---------------------------------' ||<br /> | | Channel A Tone -----------------------------------'|<br /> | |8 Channel A Amplitude Control BIT 4 3 2 1 0|<br /> | | Fixed/Variable Level (0=Fixed) -----------' | | | ||<br /> | | Amplitude level control --------------------+-+-+-'|<br /> | |9 Channel B Amplitude Control BIT 4 3 2 1 0|<br /> | | Fixed/Variable Level ---------------------' | | | ||<br /> | | Amplitude level control --------------------+-+-+-'|<br /> | |10 Channel C Amplitude Control BIT 4 3 2 1 0|<br /> | | Fixed/Variable Level ---------------------' | | | ||<br /> | | Amplitude level control --------------------+-+-+-'|<br /> | |11 Envelope Period High BIT 7 6 5 4 3 2 1 0|<br /> | |12 Envelope Period Low BIT 7 6 5 4 3 2 1 0|<br /> | |13 Envelope Shape BIT 3 2 1 0|<br /> | | Continue -----------------------------------' | | ||<br /> | | Attack ---------------------------------------' | ||<br /> | | Alternate --------------------------------------' ||<br /> | | Hold ---------------------------------------------'|<br /> | | 00xx - \____________________________________ |<br /> | | 01xx - /|___________________________________ |<br /> | | 1000 - \|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\ |<br /> | | 1001 - \____________________________________ |<br /> | | 1010 - \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ |<br /> | | 1011 - \|----------------------------------- |<br /> | | 1100 - /|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/ |<br /> | | 1101 - /------------------------------------ |<br /> | | 1110 - /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ |<br /> | | 1111 - /|___________________________________ |<br /> | |14 Port A BIT 7 6 5 4 3 2 1 0|<br /> | | IDE Drive On/OFF -------------------+ | | | | | | || (F030)<br /> | | SCC A (0=LAN, 1=Serial2) -----------' | | | | | | || (TT)<br /> | | Monitor jack GPO pin -----------------+ | | | | | ||<br /> | | Internal Speaker On/Off --------------' | | | | | || (F030)<br /> | | Centronics strobe ----------------------' | | | | ||<br /> | | RS-232 DTR output ------------------------' | | | ||<br /> | | RS-232 RTS output --------------------------' | | ||<br /> | | Drive select 1 -------------------------------' | ||<br /> | | Drive select 0 ---------------------------------' ||<br /> | | Drive side select --------------------------------'|<br /> | |15 Port B (Parallel port) |<br /> $FF8802|byte |Write data |W<br /> | +-----------------------------------------------------+<br /> | |Note: PSG Registers are now fixed at these addresses.|<br /> | |All other addresses are masked out on the Falcon. Any|<br /> | |writes to the shadow registers $8804-$88FF will cause|<br /> | |bus errors. Game/Demo coders beware! |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############DMA Sound System ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8900|byte |Buffer interrupts BIT 3 2 1 0|R/W (F030)<br /> | |TimerA-Int at end of record buffer -----------' | | ||<br /> | |TimerA-Int at end of replay buffer -------------' | ||<br /> | |MFP-15-Int (I7) at end of record buffer ----------' ||<br /> | |MFP-15-Int (I7) at end of replay buffer ------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8901|byte |DMA Control Register BIT 7 . 5 4 . . 1 0|R/W<br /> | |1 - select record register -----------+ | | | || (F030) <br /> | |0 - select replay register -----------' | | | || (F030)<br /> | |Loop record buffer -----------------------' | | || (F030)<br /> | |DMA Record on ------------------------------' | || (F030)<br /> | |Loop replay buffer -------------------------------' || (STe)<br /> | |DMA Replay on --------------------------------------'| (STe)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8903|byte |Frame start address (high byte) |R/W (STe)<br /> $FF8905|byte |Frame start address (mid byte) |R/W (STe)<br /> $FF8907|byte |Frame start address (low byte) |R/W (STe)<br /> $FF8909|byte |Frame address counter (high byte) |R (STe)<br /> $FF890B|byte |Frame address counter (mid byte) |R (STe)<br /> $FF890D|byte |Frame address counter (low byte) |R (STe)<br /> $FF890F|byte |Frame end address (high byte) |R/W (STe)<br /> $FF8911|byte |Frame end address (mid byte) |R/W (STe)<br /> $FF8913|byte |Frame end address (low byte) |R/W (STe)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8920|byte |DMA Track Control BIT 5 4 . . 1 0|R/W (F030)<br /> | |00 - Set DAC to Track 0 ------------------+-+ | ||<br /> | |01 - Set DAC to Track 1 ------------------+-+ | ||<br /> | |10 - Set DAC to Track 2 ------------------+-+ | ||<br /> | |11 - Set DAC to Track 3 ------------------+-' | ||<br /> | |00 - Play 1 Track --------------------------------+-+|<br /> | |01 - Play 2 Tracks -------------------------------+-+|<br /> | |10 - Play 3 Tracks -------------------------------+-+|<br /> | |11 - Play 4 Tracks -------------------------------+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8921|byte |Sound mode control BIT 7 6 . . . . 1 0|R/W (STe)<br /> | |0 - Stereo, 1 - Mono -----------------' | | ||<br /> | |0 - 8bit -------------------------------+ | ||<br /> | |1 - 16bit (F030 only) ------------------' | || (F030)<br /> | |Frequency control bits | ||<br /> | |00 - Off (F030 only) -----------------------------+-+| (F030)<br /> | |00 - 6258hz frequency (STe only) -----------------+-+|<br /> | |01 - 12517hz frequency ---------------------------+-+|<br /> | |10 - 25033hz frequency ---------------------------+-+|<br /> | |11 - 50066hz frequency ---------------------------+-'|<br /> | |Samples are always signed. In stereo mode, data is |<br /> | |arranged in pairs with high pair the left channel,low|<br /> | |pair right channel. Sample length MUST be even in |<br /> | |either mono or stereo mode. |<br /> | |Example: 8 bit Stereo : LRLRLRLRLRLRLRLR |<br /> | | 16 bit Stereo : LLRRLLRRLLRRLLRR (F030) |<br /> | |2 track 16 bit stereo : LLRRllrrLLRRllrr (F030) |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############STe Microwire Controller (STe/TT only!) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8922|byte |Microwire data register |R/W (Mwr)<br /> $FF8924|byte |Microwire mask register |R/W (Mwr)<br /> | +-----------------------------------------------------+<br /> | |!! ATTENTION !! Microwire is now obsolete! It is not |<br /> | |present in the Falcon030 and is unlikely to be in any|<br /> | |future machines. You have been warned. | <br /> | +-----------------------------------------------------+<br /> | |Volume/tone controller commands (Address %10)|<br /> | |Master Volume 10 011 DDDDDD|<br /> | |Left Volume 10 101 .DDDDD|<br /> | |Right Volume 10 100 .DDDDD|<br /> | |Treble 10 010 ..DDDD|<br /> | |Bass 10 001 ..DDDD|<br /> | |Mixer 10 000 ....DD|<br /> | +-----------------------------------------------------+<br /> | |Volume/tone controller values |<br /> | |Master Volume : 0-40 (0 = -80dB, 40 = 0dB) |<br /> | |Left/Right Volume : 0-20 (0 = -40dB, 20 = 0dB) |<br /> | |Treble/bass : 0-12 (0 = -12dB, 12 = +12dB) |<br /> | |Mixer : 0-3: |<br /> | | 0 = DMA only |<br /> | | 1 = DMA + YM2149 |<br /> | | 2 = DMA only |<br /> | | 3 = reserved |<br /> | | (there is no DMA + (YM2149 - 12dB) mode!) |<br /> | +-----------------------------------------------------+<br /> | |Procedure: Set mask register to $7ff. Read data |<br /> | |register and save original value.Write data register.|<br /> | |Compare data register with original value, repeat |<br /> | |until data register returns to original value to |<br /> | |ensure data has been sent over the interface. |<br /> | +-----------------------------------------------------+<br /> | |Interrupts: Timer A can be set to interrupt at the |<br /> | |end of a frame. Alternatively, the GPI7 (MFP mono |<br /> | |detect) can be used to generate interrupts thereby |<br /> | |freeing up Timer A. In this case, the active edge |<br /> | |$FFFA03 must be set by or-ing the active edge of |<br /> | |$FFFA03 with the contents of $FF8260: |<br /> | |$FF8260 - 2 (mono) or.b #$80 with edge |<br /> | |$FF8260 - 0,1 (colour) and.b #$7F with edge |<br /> | |This will generate an interrupt at the START of a |<br /> | |frame, instead of at the end as with Timer A. To |<br /> | |generate an interrupt at the END of a frame, simply |<br /> | |reverse the edge values. |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon030 DMA/DSP Controllers ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8930|word |Crossbar Source Controller |R/W (F030)<br /> | +-----------------------------------------------------+<br /> | |Source: A/D Convertor BIT 15 14 13 12|<br /> | |1 - Connect, 0 - disconnect ---------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock (Don't use) -----------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Source: External Input BIT 11 10 9 8|<br /> | |0 - DSP IN, 1 - All others ----------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock -----------------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Source: DSP-XMIT BIT 7 6 5 4|<br /> | |0 - Tristate and disconnect DSP -----------+ | | ||<br /> | | (Only for external SSI use) | | | ||<br /> | |1 - Connect DSP to multiplexer ------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock -----------------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Source: DMA-PLAYBACK BIT 3 2 1 0|<br /> | |0 - Handshaking on, dest DSP-REC ----------+ | | ||<br /> | |1 - Destination is not DSP-REC ------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock -----------------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8932|word |Crossbar Destination Controller |R/W (F030)<br /> | +-----------------------------------------------------+<br /> | |Destination: D/A Convertor BIT 15 14 13 12|<br /> | |1 - Connect, 0 - Disconnect ---------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Destination: External Output BIT 11 10 9 8|<br /> | |0 - DSP out, 1 - All others ---------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Destination: DSP-RECORD BIT 7 6 5 4|<br /> | |0 - Tristate and disconnect DSP -----------+ | | ||<br /> | | (Only for external SSI use) | | | ||<br /> | |1 - Connect DSP to multiplexer ------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Destination: DMA-RECORD BIT 3 2 1 0|<br /> | |0 - Handshaking on, src DSP-XMIT ----------+ | | ||<br /> | |1 - Source is not DSP-XMIT ----------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8934|byte |Frequency Divider External Clock BIT 3 2 1 0|R/W (F030)<br /> | |0000 - STe-Compatible mode |<br /> | |0001 - 1111 Divide by 256 and then number |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8935|byte |Frequency Divider Internal Sync BIT 3 2 1 0|R/W (F030)<br /> | |0000 - STe-Compatible mode 1000 - 10927Hz* |<br /> | |0001 - 49170Hz 1001 - 9834Hz |<br /> | |0010 - 32780Hz 1010 - 8940Hz* |<br /> | |0011 - 24585Hz 1011 - 8195Hz |<br /> | |0100 - 19668Hz 1100 - 7565Hz* |<br /> | |0101 - 16390Hz 1101 - 7024Hz* |<br /> | |0110 - 14049Hz* 1110 - 6556Hz* |<br /> | |0111 - 12292Hz 1111 - 6146Hz* |<br /> | | * - Invalid for CODEC |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8936|byte |Record Tracks Select BIT 1 0|R/W (F030)<br /> | |00 - Record 1 Track ------------------------------+-+|<br /> | |01 - Record 2 Tracks -----------------------------+-+|<br /> | |10 - Record 3 Tracks -----------------------------+-+|<br /> | |11 - Record 4 Tracks -----------------------------+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8937|byte |CODEC Input Source from 16bit adder BIT 1 0|R/W (F030)<br /> | |Source: Multiplexer ------------------------------' ||<br /> | |Source: A/D Convertor ------------------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8938|byte |CODEC ADC-Input for L+R Channel BIT 1 0|R/W (F030)<br /> | |0 - Microphone, 1 - Soundchip L R|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8939|byte |Channel amplification BIT LLLL RRRR|R/W (F030)<br /> | | Amplification is in +1.5dB steps |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF893A|word |Channel attenuation BIT LLLL RRRR|R/W (F030)<br /> | | Attenuation is in -1.5dB steps |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF893C|byte |CODEC-Status BIT 1 0|R/W (F030)<br /> | |Left Channel Overflow ----------------------------' ||<br /> | |Right Channel Overflow -----------------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8941|byte |GPx Data Direction BIT 2 1 0|R/W (F030)<br /> | |0 - In, 1 - Out --------------------------------+-+-'|<br /> | | For the GP0-GP2 pins on the DSP connector |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8943|byte |GPx Data Port BIT 2 1 0|R/W (F030)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############TT Clock Chip (MC146818A @ 32.768 khz) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8961|byte |Register select |W (TT)<br /> | |0 - Current Second |<br /> | |1 - Second for alarm |<br /> | |2 - Current Minute |<br /> | |3 - Minute for alarm |<br /> | |4 - Current Hour |<br /> | |5 - Hour for alarm |<br /> | |6 - Day of week (1=Sunday, 2=Monday, 3=...) |<br /> | |7 - Day of Month |<br /> | |8 - Month |<br /> | |9 - Year (example : '93' for this year) |<br /> | |A BIT 7|<br /> | | If set, update time in progress ----------------'|<br /> | | don't read time &amp; date registers |<br /> | |B BIT 7 6 5 4 3 2 1 0|<br /> | |1 = Write Protect time &amp; date --------' | | | | ||<br /> | |1 = Enable alarm interrupt ---------------' | | | ||<br /> | |1 = Interrupt after time updated -----------' | | ||<br /> | |1 = Format Binary, 0 = Format BCD --------------' | ||<br /> | |1 = 24hr format, 0 = 12hr format -----------------' ||<br /> | |1 = Summer hours, 0 = Winter hours -----------------'|<br /> | |C BIT 6 5 4|<br /> | | ??? -------------------------------------------' | ||<br /> | |1 = alarm is ringing -----------------------------' ||<br /> | |1 = date is updated --------------------------------'|<br /> | |On interrupt, read this register to determine source.|<br /> | |D BIT 7|<br /> | |1 = Battery dead -----------------------------------'|<br /> $FF8963|byte |Register data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Blitter (Not present on TT!) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8A00|word |Halftone-RAM, Word 0 |R/W (Blit)<br /> : | : | : : : : | : :<br /> $FF8A1E|word |Halftone-RAM, Word 15 |R/W (Blit)<br /> $FF8A20|word |Source X Increment (signed,even)|R/W (Blit)<br /> $FF8A22|word |Source Y Increment (signed,even)|R/W (Blit)<br /> $FF8A24|long |Source Address Register (24 bit,even)|R/W (Blit)<br /> $FF8A28|word |Endmask 1 (First write of a line)|R/W (Blit)<br /> $FF8A2A|word |Endmask 2 (All other line writes)|R/W (Blit)<br /> $FF8A2C|word |Endmask 3 (Last write of a line)|R/W (Blit)<br /> $FF8A2E|word |Destination X Increment (signed,even)|R/W (Blit)<br /> $FF8A30|word |Destination Y Increment (signed,even)|R/W (Blit)<br /> $FF8A32|long |Destination Address Register (24 bit,even)|R/W (Blit)<br /> $FF8A36|word |Words per Line in Bit-Block (0=65536)|R/W (Blit)<br /> $FF8A38|word |Lines per Bit-Block (0=65536)|R/W (Blit)<br /> $FF8A3A|byte |Halftone Operation Register BIT 1 0|R/W (Blit)<br /> | |00 - All ones ------------------------------------+-+|<br /> | |01 - Halftone ------------------------------------+-+|<br /> | |10 - Source --------------------------------------+-+|<br /> | |11 - Source AND Halftone -------------------------+-'|<br /> $FF8A3B|byte |Logical Operation Register BIT 3 2 1 0|R/W (Blit)<br /> | |0000 All zeros -------------------------------+-+-+-+|<br /> | |0001 Source AND destination ------------------+-+-+-+|<br /> | |0010 Source AND NOT destination --------------+-+-+-+|<br /> | |0011 Source ----------------------------------+-+-+-+|<br /> | |0100 NOT source AND destination --------------+-+-+-+|<br /> | |0101 Destination -----------------------------+-+-+-+|<br /> | |0110 Source XOR destination ------------------+-+-+-+|<br /> | |0111 Source OR destination -------------------+-+-+-+|<br /> | |1000 NOT source AND NOT destination ----------+-+-+-+|<br /> | |1001 NOT source XOR destination --------------+-+-+-+|<br /> | |1010 NOT destination -------------------------+-+-+-+|<br /> | |1011 Source OR NOT destination ---------------+-+-+-+|<br /> | |1100 NOT source ------------------------------+-+-+-+|<br /> | |1101 NOT source OR destination ---------------+-+-+-+|<br /> | |1110 NOT source OR NOT destination -----------+-+-+-+|<br /> | |1111 All ones --------------------------------+-+-+-'|<br /> $FF8A3C|byte |Line Number Register BIT 7 6 5 . 3 2 1 0|R/W (Blit)<br /> | |BUSY ---------------------------------' | | | | | ||<br /> | |0 - Share bus, 1 - Hog bus -------------' | | | | ||<br /> | |SMUDGE mode ------------------------------' | | | ||<br /> | |Halftone line number -------------------------+-+-+-'|<br /> $FF8A3D|byte |SKEW Register BIT 7 6 . . 3 2 1 0|R/W (Blit)<br /> | |Force eXtra Source Read --------------' | | | | ||<br /> | |No Final Source Read -------------------' | | | ||<br /> | |Source skew ----------------------------------+-+-+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############SCC-DMA (TT Only!) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8C01|byte |DMA Address Pointer (Highest Byte) |R/W (TT)<br /> $FF8C03|byte |DMA Address Pointer (High Byte) |R/W (TT)<br /> $FF8C05|byte |DMA Address Pointer (Low Byte) |R/W (TT)<br /> $FF8C07|byte |DMA Address Pointer (Lowest Byte) |R/W (TT)<br /> $FF8C09|byte |DMA Byte Count (Highest-Byte) |R/W (TT)<br /> $FF8C0B|byte |DMA Byte Count (High-Byte) |R/W (TT)<br /> $FF8C0D|byte |DMA Byte Count (Low-Byte) |R/W (TT)<br /> $FF8C0F|byte |DMA Byte Count (Lowest-Byte) |R/W (TT)<br /> $FF8C10|word |Residue Data Register (High-Word) |R (TT)<br /> $FF8C12|word |Residue Data register (Low-Word) |R (TT)<br /> $FF8C15|byte |Control register BIT 7 6 . . . . 1 0|R/W (TT)<br /> | |Bus error ----------------------------' | | ||<br /> | |Byte count zero ------------------------' | ||<br /> | |Enable -------------------------------------------' ||<br /> | |DMA Direction (1 - out to port) --------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Zilog 8530 SCC (MSTe/TT/F030) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8C81|byte |Channel A - Control Register |R/W (SCC)<br /> $FF8C83|byte |Channel A - Data Register |R/W (SCC)<br /> $FF8C85|byte |Channel B - Control Register |R/W (SCC)<br /> $FF8C87|byte |Channel B - Data Register |R/W (SCC)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############VME Bus System Control Unit (MSTe/TT) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E01|byte |VME sys_mask BIT 7 6 5 4 . 2 1 .|R/W (VME)<br /> $FF8E03|byte |VME sys_stat BIT 7 6 5 4 . 2 1 .|R (VME)<br /> | |_SYSFAIL in VMEBUS -------------------' | | | | | |program<br /> | |MFP ------------------------------------' | | | | |autovec<br /> | |SCC --------------------------------------' | | | |autovec<br /> | |VSYNC --------------------------------------' | | |program<br /> | |HSYNC ------------------------------------------' | |program<br /> | |System software INT ------------------------------' |program<br /> | +-----------------------------------------------------+<br /> | |Reading sys_mask resets pending int-bits in sys_stat,|<br /> | |so read sys_stat first. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E05|byte |VME sys_int BIT 0|R/W (VME)<br /> | |Setting bit 0 to 1 forces an INT of level 1. INT must|Vector $64<br /> | |be enabled in sys_mask to use it. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E0D|byte |VME vme_mask BIT 7 6 5 4 3 2 1 .|R/W (VME)<br /> $FF8E0F|byte |VME vme_stat BIT 7 6 5 4 3 2 1 .|R (VME)<br /> | |_IRQ7 from VMEBUS --------------------' | | | | | | |program<br /> | |_IRQ6 from VMEBUS/MFP ------------------' | | | | | |program<br /> | |_IRQ5 from VMEBUS/SCC --------------------' | | | | |program<br /> | |_IRQ4 from VMEBUS --------------------------' | | | |program<br /> | |_IRQ3 from VMEBUS/soft -----------------------' | | |prog/autov<br /> | |_IRQ2 from VMEBUS ------------------------------' | |program<br /> | |_IRQ1 from VMEBUS --------------------------------' |program<br /> | +-----------------------------------------------------+<br /> | |MFP-int and SCC-int are hardwired to the VME-BUS-ints|<br /> | |(or'ed). Reading vme_mask resets pending int-bits in |<br /> | |vme_stat, so read vme_stat first. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E07|byte |VME vme_int BIT 0|R/W (TT)<br /> | |Setting bit 0 to 1 forces an INT of level 3. INT must|Vector $6C<br /> | |be enabled in vme_mask to use it. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E09|byte |General purpose register - does nothing |R/W (TT)<br /> $FF8E0B|byte |General purpose register - does nothing |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Mega STe Cache/Processor Control ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E21|byte |Mega STe Cache/Processor Control BIT 15-1 0|R/W (MSTe)<br /> | |Cache enable lines (set all to 1 to enable) -----' ||<br /> | |CPU Speed (0 - 8mhz, 1 - 16mhz) --------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############DIP Switches (MSTe/TT) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF9200|byte |DIP Switches (MSTe/TT) BIT 7 6 5 4 3 2 1 0|R (MSTe/TT)<br /> | |Sound DMA active ---------------------' | ||<br /> | |Floppy Drive 1.44 HD active ------------' ||<br /> | |CaTTamaran installed -------------------------------'|<br /> | | |<br /> | |That register is mirrored by the OS in &quot;_SWI&quot; Cookie |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############STe/F030 Extended Joystick/Lightpen Ports ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF9200|word |Fire buttons 1-4 Bit 3 2 1 0|R (Ext)<br /> | |Pause/F0 -------------------------------------' | | ||<br /> | |F1 ---------------------------------------------' | ||<br /> | |F2 -----------------------------------------------' ||<br /> | |Option/F3 ------------------------------------------'|<br /> $FF9202|word |Read Mask (0 - pin read) |W (Ext)<br /> $FF9202|word |Joystick Inputs BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> | |Controller 1 pin 4 -------------------' | | | | | | ||<br /> | |Controller 1 pin 3 ---------------------' | | | | | ||<br /> | |Controller 1 pin 2 -----------------------' | | | | ||<br /> | |Controller 1 pin 1 -------------------------' | | | ||<br /> | |Controller 0 pin 4 ---------------------------' | | ||<br /> | |Controller 0 pin 3/Paddle 1 Trigger ------------' | ||<br /> | |Controller 0 pin 2/Paddle 0 Trigger --------------' ||<br /> | |Controller 0 pin 1 ---------------------------------'|<br /> | | BIT 15 14 13 12 11 10 9 8|<br /> | |Controller 1 pin 14 ------------' | | | | | | ||<br /> | |Controller 1 pin 13 ----------------' | | | | | ||<br /> | |Controller 1 pin 12 -------------------' | | | | ||<br /> | |Controller 1 pin 11 ----------------------' | | | ||<br /> | |Controller 0 pin 14 -------------------------' | | ||<br /> | |Controller 0 pin 13 ----------------------------' | ||<br /> | |Controller 0 pin 12 ------------------------------' ||<br /> | |Controller 0 pin 11 --------------------------------'|<br /> $FF9210|word |X Paddle 0 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9212|word |Y Paddle 0 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9214|word |X Paddle 1 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9216|word |Y Paddle 1 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9220|word |Lightpen X-Position BIT 9 8 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9222|word |Lightpen Y-Position BIT 9 8 7 6 5 4 3 2 1 0|R (Ext)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon VIDEL Palette Registers ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> | | BIT 33222222 22221111 11111198 76543210|<br /> | | 10987654 32109876 543210 |<br /> | | RRRRRr.. GGGGGg.. ........ BBBBBb..|<br /> $FF9800|long |Palette Register 0 Lowercase = LSB|R/W (F030)<br /> : | : | : : : | : :<br /> $FF98FC|long |Palette Register 255 |R/W (F030)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon DSP Host Interface ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFA200|byte |Interrupt Ctrl Register BIT 7 6 5 4 3 . 1 0|R/W (F030)<br /> X:$FFE9| |INIT bit -----------------------------' | | | | | ||<br /> | |00 - Interupt mode (DMA off) -----------+-+ | | | ||<br /> | |01 - 24-bit DMA mode -------------------+-+ | | | ||<br /> | |10 - 16-bit DMA mode -------------------+-+ | | | ||<br /> | |11 - 8-bit DMA mode --------------------+-' | | | ||<br /> | |Host Flag 1 --------------------------------' | | ||<br /> | |Host Flag 0 ----------------------------------' | ||<br /> | | Host mode Data transfers: | ||<br /> | | Interrupt mode | ||<br /> | |00 - No interrupts (Polling) ---------------------+-+|<br /> | |01 - RXDF Request (Interrupt) --------------------+-+|<br /> | |10 - TXDE Request (Interrupt) --------------------+-+|<br /> | |11 - RXDF and TXDE Request (Interrupts) ----------+-+|<br /> | | DMA Mode | ||<br /> | |00 - No DMA --------------------------------------+-+|<br /> | |01 - DSP to Host Request (RX) --------------------+-+|<br /> | |10 - Host to DSP Request (TX) --------------------+-+|<br /> | |11 - Undefined (Illegal) -------------------------+-'|<br /> $FFA201|byte |Command Vector Register BIT 7 . . 4 3 2 1 0|R/W (F030)<br /> X:$FFE9| |Host Command Bit (Handshake)----------' | | | | ||<br /> | |Host Vector (0-31) -------------------------+-+-+-+-'|<br /> $FFA202|byte |Interrupt Status Reg BIT 7 6 . 4 3 2 1 0|R (F030)<br /> X:$FFE8| |ISR Host Request ---------------------' | | | | | ||<br /> | |ISR DMA Status -------------------------' | | | | ||<br /> | |Host Flag 3 --------------------------------' | | | ||<br /> | |Host Flag 2 ----------------------------------' | | ||<br /> | |ISR Transmitter Ready (TRDY) -------------------' | ||<br /> | |ISR Transmit Data Register Empty (TXDE) ----------' ||<br /> | |ISR Receive Data Register Full (RXDF) --------------'|<br /> $FFA203|byte |Interrupt Vector Register |R/W (F030)<br /> $FFA204|byte |Unused | (F030)<br /> $FFA205|byte |DSP-Word High |R/W (F030)<br /> X:$FFEB| | |<br /> $FFA206|byte |DSP-Word Mid |R/W (F030)<br /> X:$FFEB| | |<br /> $FFA207|byte |DSP-Word Low |R/W (F030)<br /> X:$FFEB| | |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############MFP 68901 - Multi Function Peripheral Chip ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> | | MFP Master Clock is 2,457,600 cycles/second |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA01|byte |Parallel Port Data Register |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA03|byte |Active Edge Register BIT 7 6 5 4 . 2 1 0|R/W<br /> | |Monochrome monitor detect ------------' | | | | | | ||<br /> | |RS-232 Ring indicator ------------------' | | | | | ||<br /> | |FDC/HDC interrupt ------------------------' | | | | ||<br /> | |Keyboard/MIDI interrupt --------------------' | | | ||<br /> | |Reserved -------------------------------------' | | ||<br /> | |RS-232 CTS (input) -----------------------------' | ||<br /> | |RS-232 DCD (input) -------------------------------' ||<br /> | |Centronics busy ------------------------------------'|<br /> | +-----------------------------------------------------+<br /> | | When port bits are used for input only: |<br /> | |0 - Interrupt on pin high-low conversion |<br /> | |1 - Interrupt on pin low-high conversion |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA05|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W<br /> | |0 - In, 1 - Out ----------------------+-+-+-+-+-+-+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA07|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA0B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA0F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA13|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W<br /> | |MFP Address | | | | | | | ||<br /> | |$13C GPI7-Monochrome Detect ----------' | | | | | | ||<br /> | |$138 RS-232 Ring Detector ------------' | | | | | ||<br /> | |$134 (STe sound) Timer A --------------' | | | | ||<br /> | |$130 Receive buffer full ----------------' | | | ||<br /> | |$12C Receive error ------------------' | | ||<br /> | |$128 Send buffer empty --------------------' | ||<br /> | |$124 Send error ----------------------' ||<br /> | |$120 (HBL) Timer B ------------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA09|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA0D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA11|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA15|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W<br /> | |MFP Address | | | | | | | ||<br /> | |$11C FDC/HDC ----------' | | | | | | ||<br /> | |$118 Keyboard/MIDI ------------' | | | | | ||<br /> | |$114 (200hz clock) Timer C --------------' | | | | ||<br /> | |$110 (USART timer) Timer D ----------------' | | | ||<br /> | |$10C Blitter done ------------------' | | ||<br /> | |$108 RS-232 CTS - input --------------------' | ||<br /> | |$104 RS-232 DCD - input ----------------------' ||<br /> | |$100 Centronics Busy ------------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA17|byte |Vector Register BIT 7 6 5 4 3 . . .|R/W<br /> | |Vector Base Offset -------------------+-+-+-' | |<br /> | |1 - *Software End-interrupt mode -------------+ |<br /> | |0 - Automatic End-interrupt mode -------------' |<br /> | |* - Default operating mode |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA19|byte |Timer A Control BIT 4 3 2 1 0|R/W<br /> $FFFA1B|byte |Timer B Control BIT 4 3 2 1 0|R/W<br /> | |Reset (force output low) -------------------' | | | ||<br /> | +----------------------------------------------+-+-+-++<br /> | |0000 - Timer stop, no function executed |<br /> | |0001 - Delay mode, divide by 4 |<br /> | |0010 - : : 10 |<br /> | |0011 - : : 16 |<br /> | |0100 - : : 50 |<br /> | |0101 - : : 64 |<br /> | |0110 - : : 100 |<br /> | |0111 - Delay mode, divide by 200 |<br /> | |1000 - Event count mode |<br /> | |1xxx - Pulse extension mode, divide as above |<br /> | +-----------------------------------------------------+<br /> $FFFA1F|byte |Timer A Data |R/W<br /> $FFFA21|byte |Timer B Data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA1D|byte |Timer C &amp; D Control BIT 6 5 4 . 2 1 0|R/W<br /> | | Timer Timer|<br /> | | C D |<br /> | +-----------------------------------------------------+<br /> | |000 - Timer stop |<br /> | |001 - Delay mode, divide by 4 |<br /> | |010 - : : 10 |<br /> | |011 - : : 16 |<br /> | |100 - : : 50 |<br /> | |101 - : : 64 |<br /> | |110 - : : 100 |<br /> | |111 - Delay mode, divide by 200 |<br /> | +-----------------------------------------------------+<br /> $FFFA23|byte |Timer C Data |R/W<br /> $FFFA25|byte |Timer D Data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA27|byte |Sync Character |R/W<br /> $FFFA29|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W<br /> | |Clock divide (1 - div by 16) ---------' | | | | | | ||<br /> | |Word Length 00 - 8 bits ----------------+-+ | | | | ||<br /> | | 01 - 7 bits ----------------+-+ | | | | ||<br /> | | 10 - 6 bits ----------------+-+ | | | | ||<br /> | | 11 - 5 bits ----------------+-' | | | | ||<br /> | |Bits Stop Start Format | | | | ||<br /> | |00 0 0 Synchronous ----------------+-+ | | ||<br /> | |01 1 1 Asynchronous ---------------+-+ | | ||<br /> | |10 1 1.5 Asynchronous ---------------+-+ | | ||<br /> | |11 1 2 Asynchronous ---------------+-' | | ||<br /> | |Parity (0 - ignore parity bit) -----------------' | ||<br /> | |Parity (0 - odd parity,1 - even) -----------------' ||<br /> | |Unused ---------------------------------------------'|<br /> $FFFA2B|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W<br /> | |Buffer full --------------------------' | | | | | | ||<br /> | |Overrun error --------------------------' | | | | | ||<br /> | |Parity error -----------------------------' | | | | ||<br /> | |Frame error --------------------------------' | | | ||<br /> | |Found - Search/Break detected ----------------' | | ||<br /> | |Match/Character in progress --------------------' | ||<br /> | |Synchronous strip enable -------------------------' ||<br /> | |Receiver enable bit --------------------------------'|<br /> $FFFA2D|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W<br /> | |Buffer empty -------------------------' | | | | | | ||<br /> | |Underrun error -------------------------' | | | | | ||<br /> | |Auto turnaround --------------------------' | | | | ||<br /> | |End of transmission ------------------------' | | | ||<br /> | |Break ----------------------------------------' | | ||<br /> | |High bit ---------------------------------------' | ||<br /> | |Low bit ------------------------------------------' ||<br /> | |Transmitter enable ---------------------------------'|<br /> $FFFA2F|byte |USART data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Floating Point Coprocessor (CIR Interface in MSTe) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA40|word |FP_Stat Response-Register |??? (MSTe)<br /> $FFFA42|word |FP_Ctl Control-Register |??? (MSTe)<br /> $FFFA44|word |FP_Save Save-Register |??? (MSTe)<br /> $FFFA46|word |FP_Restor Restore-Register |??? (MSTe)<br /> $FFFA48|word | |??? (MSTe)<br /> $FFFA4A|word |FP_Cmd Command-Register |??? (MSTe)<br /> $FFFA4E|word |FP_Ccr Condition-Code-Register |??? (MSTe)<br /> $FFFA50|long |FP_Op Operand-Register |??? (MSTe)<br /> $FFFA54|word |FP_Selct Register Select |??? (MSTe)<br /> $FFFA58|long |FP_Iadr Instruction Address |??? (MSTe)<br /> $FFFA5C|long | Operand Address |??? (MSTe)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############MFP 68901 #2 (MFP2) - TT Only ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA81|byte |Parallel Port Data Register |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA83|byte |Active Edge Register BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | +-----------------------------------------------------+<br /> | | When port bits are used for input only: |<br /> | |0 - Interrupt on pin high-low conversion |<br /> | |1 - Interrupt on pin low-high conversion |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA85|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |0 - In, 1 - Out ----------------------+-+-+-+-+-+-+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA87|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA8B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA8F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA93|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |MFP Address | | | | | | | ||<br /> | |$17C TT-SCSI NCR5380 ---------' | | | | | | ||<br /> | |$178 RTC (MC146818A) -----------' | | | | | ||<br /> | |$174 Timer A -------------' | | | | ||<br /> | |$170 Receive buffer full ---------------' | | | ||<br /> | |$16C Receive error -----------------' | | ||<br /> | |$168 Send buffer empty -------------------' | ||<br /> | |$164 Send error ---------------------' ||<br /> | |$160 Timer B -----------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA89|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA8D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA91|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA95|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |MFP Address | | | | | | | ||<br /> | |$15C SCSI DMA Controller ---------' | | | | | | ||<br /> | |$158 (Reserved) GPIP 4 -----------' | | | | | ||<br /> | |$154 Timer C -------------' | | | | ||<br /> | |$150 Timer D ---------------' | | | ||<br /> | |$14C SCC B Ring Indicator -----------------' | | ||<br /> | |$148 SCC DMA Controller -------------------' | ||<br /> | |$144 General Purpose Input 1 ---------------------' ||<br /> | |$140 General Purpose Input 0 -----------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA97|byte |Vector Register BIT 7 6 5 4 3 . . .|R/W (TT)<br /> | |Vector Base Offset -------------------+-+-+-' | |<br /> | |1 - *Software End-interrupt mode -------------+ |<br /> | |0 - Automatic End-interrupt mode -------------' |<br /> | |* - Default operating mode |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA99|byte |Timer A Control BIT 4 3 2 1 0|R/W (TT)<br /> $FFFA9B|byte |Timer B Control BIT 4 3 2 1 0|R/W (TT)<br /> | |Reset (force output low) -------------------' | | | ||<br /> | +----------------------------------------------+-+-+-++<br /> | |0000 - Timer stop, no function executed |<br /> | |0001 - Delay mode, divide by 4 |<br /> | |0010 - : : 10 |<br /> | |0011 - : : 16 |<br /> | |0100 - : : 50 |<br /> | |0101 - : : 64 |<br /> | |0110 - : : 100 |<br /> | |0111 - Delay mode, divide by 200 |<br /> | |1000 - Event count mode |<br /> | |1xxx - Pulse extension mode, divide as above |<br /> | +-----------------------------------------------------+<br /> $FFFA9F|byte |Timer A Data |R/W (TT)<br /> $FFFAA1|byte |Timer B Data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA9D|byte |Timer C &amp; D Control BIT 6 5 4 . 2 1 0|R/W (TT)<br /> | | Timer Timer|<br /> | | C D |<br /> | +-----------------------------------------------------+<br /> | |000 - Timer stop |<br /> | |001 - Delay mode, divide by 4 |<br /> | |010 - : : 10 |<br /> | |011 - : : 16 |<br /> | |100 - : : 50 |<br /> | |101 - : : 64 |<br /> | |110 - : : 100 |<br /> | |111 - Delay mode, divide by 200 |<br /> | +-----------------------------------------------------+<br /> $FFFAA3|byte |Timer C Data |R/W (TT)<br /> $FFFAA5|byte |Timer D Data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFAA7|byte |Sync Character |R/W (TT)<br /> $FFFAA9|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W (TT)<br /> | |Clock divide (1 - div by 16) ---------' | | | | | | ||<br /> | |Word Length 00 - 8 bits ----------------+-+ | | | | ||<br /> | | 01 - 7 bits ----------------+-+ | | | | ||<br /> | | 10 - 6 bits ----------------+-+ | | | | ||<br /> | | 11 - 5 bits ----------------+-' | | | | ||<br /> | |Bits Stop Start Format | | | | ||<br /> | |00 0 0 Synchronous ----------------+-+ | | ||<br /> | |01 1 1 Asynchronous ---------------+-+ | | ||<br /> | |10 1 1.5 Asynchronous ---------------+-+ | | ||<br /> | |11 1 2 Asynchronous ---------------+-' | | ||<br /> | |Parity (0 - ignore parity bit) -----------------' | ||<br /> | |Parity (0 - odd parity,1 - even) -----------------' ||<br /> | |Unused ---------------------------------------------'|<br /> $FFFAAB|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |Buffer full --------------------------' | | | | | | ||<br /> | |Overrun error --------------------------' | | | | | ||<br /> | |Parity error -----------------------------' | | | | ||<br /> | |Frame error --------------------------------' | | | ||<br /> | |Found - Search/Break detected ----------------' | | ||<br /> | |Match/Character in progress --------------------' | ||<br /> | |Synchronous strip enable -------------------------' ||<br /> | |Receiver enable bit --------------------------------'|<br /> $FFFAAD|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |Buffer empty -------------------------' | | | | | | ||<br /> | |Underrun error -------------------------' | | | | | ||<br /> | |Auto turnaround --------------------------' | | | | ||<br /> | |End of transmission ------------------------' | | | ||<br /> | |Break ----------------------------------------' | | ||<br /> | |High bit ---------------------------------------' | ||<br /> | |Low bit ------------------------------------------' ||<br /> | |Transmitter enable ---------------------------------'|<br /> $FFFAAF|byte |USART data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############6850 ACIA I/O Chips ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFC00|byte |Keyboard ACIA control BIT 7 6 5 4 3 2 1 0|W<br /> | |Rx Int enable (1 - enable) -----------' | | | | | | ||<br /> | |Tx Interrupts | | | | | | ||<br /> | |00 - RTS low, Tx int disable -----------+-+ | | | | ||<br /> | |01 - RTS low, Tx int enable ------------+-+ | | | | ||<br /> | |10 - RTS high, Tx int disable ----------+-+ | | | | ||<br /> | |11 - RTS low, Tx int disable, | | | | | | ||<br /> | | Tx a break onto data out ----------+-' | | | | ||<br /> | |Settings | | | | ||<br /> | |000 - 7 bit, even, 2 stop bit --------------+-+-+ | ||<br /> | |001 - 7 bit, odd, 2 stop bit ---------------+-+-+ | ||<br /> | |010 - 7 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |011 - 7 bit, odd, 1 stop bit ---------------+-+-+ | ||<br /> | |100 - 8 bit, 2 stop bit --------------------+-+-+ | ||<br /> | |101 - 8 bit, 1 stop bit --------------------+-+-+ | ||<br /> | |110 - 8 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |111 - 8 bit, odd, 1 stop bit ---------------+-+-' | ||<br /> | |Clock divide | ||<br /> | |00 - Normal --------------------------------------+-+|<br /> | |01 - Div by 16 -----------------------------------+-+|<br /> | |10 - Div by 64 -----------------------------------+-+|<br /> | |11 - Master reset --------------------------------+-'|<br /> $FFFC00|byte |Keyboard ACIA control BIT 7 6 5 4 3 2 1 0|R<br /> | |Interrupt request --------------------' | | | | | | ||<br /> | |Parity error ---------------------------' | | | | | ||<br /> | |Rx overrun -------------------------------' | | | | ||<br /> | |Framing error ------------------------------' | | | ||<br /> | |CTS ------------------------------------------' | | ||<br /> | |DCD --------------------------------------------' | ||<br /> | |Tx data register empty ---------------------------' ||<br /> | |Rx data register full ------------------------------'|<br /> $FFFC02|byte |Keyboard ACIA data |R/W<br /> $FFFC04|byte |MIDI ACIA control BIT 7 6 5 4 3 2 1 0|W<br /> | |Rx Int enable (1 - enable) -----------' | | | | | | ||<br /> | |Tx Interrupts | | | | | | ||<br /> | |00 - RTS low, Tx int disable -----------+-+ | | | | ||<br /> | |01 - RTS low, Tx int enable ------------+-+ | | | | ||<br /> | |10 - RTS high, Tx int disable ----------+-+ | | | | ||<br /> | |11 - RTS low, Tx int disable, | | | | | | ||<br /> | | Tx a break onto data out ----------+-' | | | | ||<br /> | |Settings | | | | ||<br /> | |000 - 7 bit, even, 2 stop bit --------------+-+-+ | ||<br /> | |001 - 7 bit, odd, 2 stop bit ---------------+-+-+ | ||<br /> | |010 - 7 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |011 - 7 bit, odd, 1 stop bit ---------------+-+-+ | ||<br /> | |100 - 8 bit, 2 stop bit --------------------+-+-+ | ||<br /> | |101 - 8 bit, 1 stop bit --------------------+-+-+ | ||<br /> | |110 - 8 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |111 - 8 bit, odd, 1 stop bit ---------------+-+-' | ||<br /> | |Clock divide | ||<br /> | |00 - Normal --------------------------------------+-+|<br /> | |01 - Div by 16 -----------------------------------+-+|<br /> | |10 - Div by 64 -----------------------------------+-+|<br /> | |11 - Master reset --------------------------------+-'|<br /> $FFFC04|byte |MIDI ACIA control BIT 7 6 5 4 3 2 1 0|R<br /> | |Interrupt request --------------------' | | | | | | ||<br /> | |Parity error ---------------------------' | | | | | ||<br /> | |Rx overrun -------------------------------' | | | | ||<br /> | |Framing error ------------------------------' | | | ||<br /> | |CTS ------------------------------------------' | | ||<br /> | |DCD --------------------------------------------' | ||<br /> | |Tx data register empty ---------------------------' ||<br /> | |Rx data register full ------------------------------'|<br /> $FFFC06|byte |MIDI ACIA data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Realtime Clock ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFC21|byte |S_Units |???<br /> $FFFC23|byte |S_Tens |???<br /> $FFFC25|byte |M_Units |???<br /> $FFFC27|byte |M_Tens |???<br /> $FFFC29|byte |H_Units |???<br /> $FFFC2B|byte |H_Tens |???<br /> $FFFC2D|byte |Weekday |???<br /> $FFFC2F|byte |Day_Units |???<br /> $FFFC31|byte |Day_Tens |???<br /> $FFFC33|byte |Mon_Units |???<br /> $FFFC35|byte |Mon_Tens |???<br /> $FFFC37|byte |Yr_Units |???<br /> $FFFC39|byte |Yr_Tens |???<br /> $FFFC3B|byte |Cl_Mod |???<br /> $FFFC3D|byte |Cl_Test |???<br /> $FFFC3F|byte |Cl_Reset |???<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############ROM ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FA0000| | |<br /> : | |128K ROM expansion cartridge port |R<br /> $FBFFFF| | |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FC0000| | |<br /> : | |192K System ROM |R<br /> $FEFFFF| | |<br /> -------+-----+-----------------------------------------------------+----------<br /> <br /> Atari 32 bit Memory Map<br /> <br /> Addresses Description<br /> -------------------+----------------------------------------------------------<br /> $00000000-$00DFFFFF|ST RAM<br /> $00E00000-$00EFFFFF|512k TOS ROMs<br /> $00F00000-$00F9FFFF|Reserved I/O Space<br /> $00FA0000-$00FBFFFF|128k ROM cartridge expansion port<br /> $00FC0000-$00FEFFFF|192k System ROM<br /> $00FF0000-$00FF7FFF|Reserved I/O Space<br /> $00FF8000-$00FFFFFF|ST/TT I/O<br /> $01000000-$013FFFFF|TT Fast Ram<br /> $01400000-$FDFFFFFF|Reserved<br /> $FE000000-$FEFFFFFF|VME A24/D16<br /> $FEFF0000-$FEFFFFFF|VME A16/D16<br /> $FF000000-$FFFFFFFF|ST 24 bit compatible shadow<br /> $FFD000xx-$FFD000xx|Set FastRAM refresh rate and generate a bus error<br /> -------------------+----------------------------------------------------------<br /> <br /> Cookie Jar<br /> Atari &quot;Official&quot; Cookies<br /> Cookie Description<br /> -------+----------------------------------------------------------------------<br /> _CPU | CPU Type Bit 7 6 5 4 3 2 1 0<br /> | Processor type is represented in decimal in the lowest byte.<br /> | (0 - 68000, 40 - 68040)<br /> -------+----------------------------------------------------------------------<br /> _VDO | Video Type BIT 17 16<br /> | Shifter Type | |<br /> | 00 - ST ---------------------------------------------------------+--+<br /> | 01 - STe --------------------------------------------------------+--+<br /> | 10 - TT ---------------------------------------------------------+--+<br /> | 11 - Falcon030 --------------------------------------------------+--'<br /> -------+----------------------------------------------------------------------<br /> _FDC | Floppy Drive Controller BIT 25 24 . 23-0<br /> | Floppy Format | | |<br /> | 00 - DD (Normal floppy interface) ------------------------+--+ |<br /> | 01 - HD (1.44 MB with 3.5&quot;) ------------------------------+--+ |<br /> | 10 - ED (2.88 MB with 3.5&quot;) ------------------------------+--' |<br /> | Controller ID |<br /> | 0 - No information available |<br /> | 'ATC' - Fully compatible interface built in a way that -------------+<br /> | behaves like part of the system. |<br /> | 'DP1' - &quot;DreamPark Development&quot;, all ID's beginning with -----------'<br /> | &quot;DP&quot; are reserved for Dreampark.<br /> -------+----------------------------------------------------------------------<br /> _FLK | File Locking<br /> | If present, GEMDOS supports file locking. Value represents version<br /> | number of the expansion.<br /> -------+----------------------------------------------------------------------<br /> _NET | Network Type<br /> | If present, there is GEMDOS network support. Points to 2 longs:<br /> | The first is the ID of the producer, and the second is the version<br /> | number.<br /> -------+----------------------------------------------------------------------<br /> _SLM | SLM Driver<br /> | Diablo-driver for the SLM laser printer. Value points to a<br /> | non-documented structure.<br /> -------+----------------------------------------------------------------------<br /> _INF | .INF Patch<br /> | When present, STEFIX (patch program for TOS 1.06) is active.<br /> -------+----------------------------------------------------------------------<br /> _SND | Sound Hardware BIT 5 4 3 2 1 0<br /> | CodeC (??) -----------------------------------------------' | | | | |<br /> | Connection Matrix ------------------------------------------' | | | |<br /> | DSP56001 -----------------------------------------------------' | | |<br /> | 16 Bit DMA Sound -----------------------------------------------' | |<br /> | 8 Bit DMA Sound --------------------------------------------------' |<br /> | YM2149 -------------------------------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> _MCH | Machine Type BIT 17 16<br /> | 00 - ST/Mega ST -------------------------------------------------+--+<br /> | 01 - STe &amp; Compatible Machines (See Below) ----------------------+--+<br /> | 10 - TT ---------------------------------------------------------+--+<br /> | 11 - Falcon030 --------------------------------------------------+--'<br /> | STe &amp; Compatible Machines BIT 5 4 3 2 1 0<br /> | 00000 - STe ----------------------------------------------+-+-+-+-+-+<br /> | 00001 - ST Book ------------------------------------------+-+-+-+-+-+<br /> | 10000 - Mega STe -----------------------------------------+-+-+-+-+-'<br /> -------+----------------------------------------------------------------------<br /> _SWI | Configuration Switches<br /> | State of configuration switches (MSTe/TT only)<br /> -------+----------------------------------------------------------------------<br /> _FRB | Fast Ram Buffer<br /> | (TT specific) 64k buffer for ACSI DMA<br /> | 0 - no buffers assigned Not 0 - address of FastRam buffer<br /> -------+----------------------------------------------------------------------<br /> _FPU | FPU Type<br /> | Software FPU BIT 3 2 1 0<br /> | 68040's internal FPU -----------------------------------------' | | |<br /> | 01 - 6888x present ---------------------------------------------+-+ |<br /> | 10 - 68881 for sure --------------------------------------------+-+ |<br /> | 11 - 68882 for sure --------------------------------------------+-' |<br /> | SFP004 present -----------------------------------------------------'<br /> | Hardware FPU BIT 11 10 9 8<br /> | 68040's internal FPU ----------------------------------------' | | |<br /> | 01 - 6888x present ---------------------------------------------+-+ |<br /> | 10 - 68881 for sure --------------------------------------------+-+ |<br /> | 11 - 68882 for sure --------------------------------------------+-' |<br /> | SFP004 present -----------------------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> _OOL | PoolFix<br /> | Value corresponds to PoolFix version<br /> -------+----------------------------------------------------------------------<br /> _AKP | Keyboard/Language Configuration<br /> | Keyboard Configuration Bit 15-8<br /> | 1 - German 5 - Italian -------------------------------------------+<br /> | 2 - French 7 - Swiss French --------------------------------------+<br /> | 4 - Spanish 8 - Swiss German --------------------------------------+<br /> | All others - English -----------------------------------------------'<br /> | Language Configuration BIT 7-0<br /> | 1 - German 5 - Italian -------------------------------------------+<br /> | 2 - French 7 - Swiss French --------------------------------------+<br /> | 4 - Spanish 8 - Swiss German --------------------------------------+<br /> | All others - English -----------------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> _IDT | International Date/Time Format<br /> | Time Format BIT 12<br /> | 0 - AM/PM, 1 - 24 hours --------------------------------------------+<br /> | Date Format BIT 9 8<br /> | 00 - MMDDYY ------------------------------------------------------+-+<br /> | 01 - DDMMYY ------------------------------------------------------+-+<br /> | 10 - YYMMDD ------------------------------------------------------+-+<br /> | 11 - YYDDMM ------------------------------------------------------+-'<br /> | Separator for date BIT 7-0<br /> | ASCII Value (i.e. &quot;.&quot; or &quot;/&quot;) --------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> MiNT | MiNT<br /> | Present if MiNT/MultiTOS is active. Value represents the version<br /> | number of the MiNT kernel in hex (0x104 = 1.04)<br /> -------+----------------------------------------------------------------------<br /> &lt;/pre&gt;<br /> <br /> [[Category:Programming]]<br /> [[Category:Memory Address]]</div>

Cyprian https://www.temlib.org/AtariForumWiki/index.php?title=Atari_ST/STe/MSTe/TT/F030_Hardware_Register_Listing&diff=22856 2023-06-09T14:47:14Z

<p>Cyprian: some updates/corrections known in 2023</p> <hr /> <div>Based on:<br /> * https://temlib.org/AtariForumWiki/index.php/Atari_ST/STe/MSTe/TT/F030_Hardware_Register_Listing<br /> * https://github.com/Number0000009/atari-wiki/blob/master/Atari%20ST%20STe%20MSTe%20TT%20F030%20Hardware%20Register%20Listing.txt<br /> * https://mikro.naprvyraz.sk/docs/Memory%20Maps/FALREG.TXT<br /> * https://mikro.naprvyraz.sk/docs/mikro/videl.html<br /> * http://cd.textfiles.com/atarilibrary/atari_cd10/DISKS/AC10DISK/ATOZBOOK/M.TXT<br /> <br /> &lt;pre&gt;<br /> .---------------------------------------------------.<br /> |Atari ST/STe/MSTe/TT/F030 Hardware Register Listing|<br /> `---------------------------------------------------'<br /> <br /> <br /> <br /> Address Description Space<br /> -------+----------------------------------------------------------------+-----<br /> ########CPU Reset Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $000000|Reset : Initial SSP |SP<br /> $000004|Reset : Initial PC |SP<br /> -------+----------------------------------------------------------------+-----<br /> ########CPU Exception Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $000008|Bus Error |SD<br /> $00000C|Address Error |SD<br /> $000010|Illegal Instruction |SD<br /> $000014|Zero Divide |SD<br /> $000018|CHK, CHK2 Instruction |SD<br /> $00001C|cpTRAPcc, TRAPcc, TRAPV |SD<br /> $000020|Privilege Violation |SD<br /> $000024|Trace |SD<br /> $000028|Line 1010 Emulator (LineA) |SD<br /> $00002C|Line 1111 Emulator (LineF) |SD<br /> $000030|(Unassigned, Reserved) |SD<br /> $000034|Coprocessor Protocol Violation (68030) |SD<br /> $000038|Format Error (68010) |SD<br /> $00003C|Uninitialized Interrupt Vector |SD<br /> $000040|(Unassigned, Reserved) |SD<br /> : | : : | :<br /> $00005F|(Unassigned, Reserved) |SD<br /> $000060|Spurious Interrupt (Bus error during interrupt) |SD <br /> -------+----------------------------------------------------------------+-----<br /> ########Auto-Vector Interrupts ######<br /> -------+----------------------------------------------------------------+-----<br /> $000064|Level 1 Int Autovector (TT VME) |SD<br /> $000068|Level 2 Int Autovector (HBL) |SD<br /> $00006C|Level 3 Int Autovector (TT VME) |SD<br /> $000070|Level 4 Int Autovector (VBL) |SD<br /> $000074|Level 5 Int Autovector |SD<br /> $000078|Level 6 Int Autovector (MFP) |SD<br /> $00007C|Level 7 Int Autovector |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########Trap Instruction Vectors (Trap #n = Vector number + 32 + n) ######<br /> -------+----------------------------------------------------------------+-----<br /> $000080|Trap #0 |SD<br /> $000084|Trap #1 (GemDOS) |SD<br /> $000088|Trap #2 (AES/VDI) |SD<br /> $00008C|Trap #3 |SD<br /> $000090|Trap #4 |SD<br /> $000094|Trap #5 |SD<br /> $000098|Trap #6 |SD<br /> $00009C|Trap #7 |SD<br /> $0000A0|Trap #8 |SD<br /> $0000A4|Trap #9 |SD<br /> $0000A8|Trap #10 |SD<br /> $0000AC|Trap #11 |SD<br /> $0000B0|Trap #12 |<br /> $0000B4|Trap #13 (BIOS) |SD<br /> $0000B8|Trap #14 (XBIOS) |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########Math Coprocessor Vectors (68881/68882/Internal) ######<br /> -------+----------------------------------------------------------------+-----<br /> $0000C0|FFCP Branch or Set on Unordered Condition |SD<br /> $0000C4|FFCP Inexact Result |SD<br /> $0000C8|FFCP Divide by Zero |SD<br /> $0000CC|FFCP Underflow |SD<br /> $0000D0|FFCP Operand Error |SD<br /> $0000D4|FFCP Overflow |SD<br /> $0000D8|FFCP Signaling NAN |SD<br /> $0000DC|(Unassigned, Reserved) |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########PMMU Coprocessor Vectors (68851/Internal) ######<br /> -------+----------------------------------------------------------------+-----<br /> $0000E0|MMU Configuration Error |SD<br /> $0000E4|MC68851, not used by MC68030 |SD<br /> $0000E8|MC68851, not used by MC68030 |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########Miscellaneous Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $0000EC|(Unassigned, Reserved) |SD<br /> : | : : | :<br /> $0000FF|(Unassigned, Reserved) |SD<br /> -------+----------------------------------------------------------------+-----<br /> ########User Assigned Interrupt Vectors ######<br /> -------+----------------------------------------------------------------+-----<br /> $000100|ST-MFP-0 - Centronics busy |SD<br /> $000104|ST-MFP-1 - RS-232 DCD |SD<br /> $000108|ST-MFP-2 - RS-232 CTS |SD<br /> $00010C|ST-MFP-3 - Blitter done |SD<br /> $000110|ST-MFP-4 - Timer D (USART timer) |SD<br /> $000114|ST-MFP-5 - Timer C (200hz Clock) |SD<br /> $000118|ST-MFP-6 - Keyboard/MIDI (ACIA) |SD<br /> $00011C|ST-MFP-7 - FDC/HDC |SD<br /> $000120|ST-MFP-8 - Timer B (HBL) |SD<br /> $000124|ST-MFP-9 - Send Error |SD<br /> $000128|ST-MFP-10 - Send buffer empty |SD<br /> $00012C|ST-MFP-11 - Receive error |SD<br /> $000130|ST-MFP-12 - Receive buffer full |SD<br /> $000134|ST-MFP-13 - Timer A (STe sound) |SD<br /> $000138|ST-MFP-14 - RS-232 Ring detect |SD<br /> $00013C|ST-MFP-15 - GPI7 - Monochrome Detect |SD<br /> $000140|TT-MFP-0 - GPI 0 |SD<br /> $000144|TT-MFP-1 - GPI 1 |SD<br /> $000148|TT-MFP-2 - SCC-DMA Controller |SD<br /> $00014C|TT-MFP-3 - Ring Indicator SCC B |SD<br /> $000150|TT-MFP-4 - Timer D |SD<br /> $000154|TT-MFP-5 - Timer C |SD<br /> $000158|TT-MFP-6 - (Reserved) GPI 4 |SD<br /> $00015C|TT-MFP-7 - SCSI DMA Controller |SD<br /> $000160|TT-MFP-8 - Timer B |SD<br /> $000164|TT-MFP-9 - Send Error |SD<br /> $000168|TT-MFP-10 - Send buffer empty |SD<br /> $00016C|TT-MFP-11 - Receive error |SD<br /> $000170|TT-MFP-12 - Receive buffer full |SD<br /> $000174|TT-MFP-13 - Timer A |SD<br /> $000176|TT-MFP-14 - TT Clock (MC146818A) |SD<br /> $00017C|TT-MFP-15 - TT-SCSI Drive Controller NCR 5380 |SD<br /> $000180|SCC Interrupt |SD<br /> $0001BC|SCC Interrupt |SD<br /> $0001C0|User Defined, Unused |SD<br /> : | : : : | :<br /> $0003FC|User Defined, Unused |SD<br /> -------+----------------------------------------------------------------+-----<br /> <br /> Address Size Description Name<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############System Crash Page ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $000380|long |Validates System Crash Page if $12345678 |proc_lives<br /> $000384|.....|Saved registers D0-D7 |proc_dregs<br /> $0003A4|.....|Saved registers A0-A7 |proc_aregs<br /> $0003C4|long |Vector number of crash exception |proc_enum<br /> $0003C8|long |Saved USP |proc_usp<br /> $0003CC|.....|Saved 16 words from exception stack |proc_stk<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############System Variables ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $000400|long |GEM Event timer vector |etv_timer<br /> $000404|long |GEM Critical error handler |etv_critic<br /> $000408|long |GEM Program termination vector |etv_term<br /> $00040C|long |GEM Additional vector #1 (Unused) |etv_xtra<br /> : | : | : : : : : | :<br /> $00041C|long |GEM Additional vector #5 (Unused) |etv_xtra<br /> $000420|long |Validates memory configuration if $752019F3 |memvalid<br /> $000424|word |Copy of contents of $FF8001 |memctrl<br /> $000426|long |Validates resvector if $31415926 |resvalid<br /> $00042A|long |Reset vector |resvector<br /> $00042E|long |Physical top of RAM |phystop<br /> $000432|long |Start of TPA (user memory) |_membot<br /> $000436|long |End of TPA (user memory) |_memtop<br /> $00043A|long |Validates memcntrl and memconf if $237698AA |memval2<br /> $00043E|word |If nonzero, floppy disk VBL routine is disabled |flock<br /> $000440|word |Floppy Seek rate - 0:6ms, 1:12ms, 2:2ms, 3:3ms |seekrate<br /> $000442|word |Time between two timer calls (in milliseconds) |_timer_ms<br /> $000444|word |If not zero, verify floppy disk writes |_fverify<br /> $000446|word |Default boot device |_bootdev<br /> $000448|word |0 - NTSC (60hz), &lt;&gt;0 - PAL (50hz) |palmode<br /> $00044A|word |Default video resolution |defshiftmod<br /> $00044C|word |Copy of contents of $FF8260 |sshiftmod<br /> $00044E|long |Pointer to video RAM (logical screen base) |_v_bas_ad<br /> $000452|word |If not zero, VBL routine is not executed |vblsem<br /> $000454|word |Number of vertical blank routines |nvbls<br /> $000456|long |Pointer to list of vertical blank routines |_vblqueue<br /> $00045A|long |If not zero, points to color palette to be loaded |colorptr<br /> $00045E|long |If not zero, points to video ram for next VBL |screenpt<br /> $000462|long |Counter for number of VBLs |_vbclock<br /> $000466|long |Number of VBL routines executed |_frclock<br /> $00046A|long |Vector for hard disk initialization |hdv_init<br /> $00046E|long |Vector for resolution change |swv_vec<br /> $000472|long |Vector for getbpb for hard disk |hdv_bpb<br /> $000476|long |Vector for read/write routine for hard disk |hdv_rw<br /> $00047A|long |Vector for hard disk boot |hdv_boot<br /> $00047E|long |Vector for hard disk media change |hdv_mediach<br /> $000482|word |If not zero, attempt to load &quot;COMMAND.PRG&quot; on boot |_comload<br /> $000484|byte |Attribute vector for console output BIT 3 2 1 0|conterm<br /> | |Return &quot;kbshift&quot; for BIOS conin --------------' | | ||<br /> | |System bell (1 - on) ---------------------------' | ||<br /> | |Key repeat (1 - on) ------------------------------' ||<br /> | |Key click (1 - on) ---------------------------------'|<br /> $000486|long |Return address for TRAP #14 (unused)|trp14ret<br /> $00048A|long |Return address for critical error handler (unused)|criticret<br /> $00048E|long |Memory descriptor block |themd<br /> $00049E|long |Space for additional memory descriptors |themdmd<br /> $0004A2|long |Pointer to BIOS save registers block |savptr<br /> $0004A6|word |Number of connected floppy drives |_nflops<br /> $0004A8|long |Vector for screen output |con_state<br /> $0004AC|word |Temporary storage for cursor line position |save_row<br /> $0004AE|long |Pointer to save area for exception processing |sav_context<br /> $0004B2|long |Pointer to buffer control block for GEMDOS data |_bufl<br /> $0004B6|long |Pointer to buffer control block for GEMDOS fat/dir |_bufl<br /> $0004BA|long |Counter for 200hz system clock |_hz_200<br /> $0004BC|long |Pointer to default environment string |the_env<br /> $0004C2|long |Bit allocation for physical drives (bit 0=A, 1=B..) |_drvbits<br /> $0004C6|long |Pointer to 1024-byte disk buffer |_dskbufp<br /> $0004CA|long |Pointer to autoexecute path |_autopath<br /> $0004CE|long |Pointer to VBL routine #1 |_vbl_lis<br /> : | : | : : : : : | :<br /> $0004EA|long |Pointer to VBL routine #8 |_vbl_lis<br /> $0004EE|word |Flag for screen -&gt; printer dump |_dumpflg<br /> $0004F0|word |Printer abort flag |_prtabt<br /> $0004F2|long |Pointer to start of OS |_sysbase<br /> $0004F6|long |Global shell pointer |_shell_p<br /> $0004FA|long |Pointer to end of OS |end_os<br /> $0004FE|long |Pointer to entry point of OS |exec_os<br /> $000502|long |Pointer to screen dump routine |scr_dump<br /> $000506|long |Pointer to _lstostat() |prv_lsto<br /> $00050A|long |Pointer to _lstout() |prv_lst<br /> $00050E|long |Pointer to _auxostat() |prv_auxo<br /> $000512|long |Pointer to _auxout() |prv_aux<br /> $000516|long |If AHDI, pointer to pun_info |pun_ptr<br /> $00051A|long |If $5555AAAA, reset |memval3<br /> $00051E|long |8 Pointers to input-status routines |xconstat<br /> $00053E|long |8 Pointers to input routines |xconin<br /> $00055E|long |8 Pointers to output-status routines |xcostat<br /> $00057E|long |8 Pointers to output routines |xconout<br /> $00059E|word |If not 0, then not 68000 - use long stack frames |_longframe<br /> $0005A0|long |Pointer to cookie jar |_p_cookies<br /> $0005A4|long |Pointer to end of FastRam |ramtop<br /> $0005A8|long |Validates ramtop if $1357BD13 |ramvalid<br /> $0005AC|long |Pointer to routine for system bell |bell_hook<br /> $0005B0|long |Pointer to routine for system keyclick |kcl_hook<br /> -------+-----+-----------------------------------------------------+----------<br /> <br /> Address Size Description Bits used Read/Write<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############OS ROMs ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $E00000|byte |TOS 512k ROMs |R<br /> : | : | : : : |:<br /> $EFFFFF|byte |TOS 512k ROMs |R<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############ADSPEED Configuration registers ########### <br /> -------+-----+-----------------------------------------------------+----------<br /> $F00000|byte |Switch to 16 Mhz |W<br /> $F10000|byte |Switch to 8 Mhz |W<br /> $F20000|byte |Turn on high speed ROM option in 16 Mhz |W<br /> $F30000|byte |Turn off high speed ROM option |W<br /> $F40000|byte |Unknown |W<br /> $F50000|byte |Turn off cache while in 16 Mhz |W<br /> | | &gt;&gt; Write 0 to an address to set it. &lt;&lt; |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############IDE Controller (Falcon, ST-Book, IDE cards) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $F00000|word |Data Register |R/W<br /> | | BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0|<br /> $F00002|word |Data Register |R/W<br /> | | BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0|<br /> $F00005|byte |Error Register BIT 7 6 5 4 3 2 1 0|R<br /> | |Bad block mark -----------------------' | | | | | | ||<br /> | |Uncorrectable error --------------------' | | | | | ||<br /> | |Media change -----------------------------' | | | | ||<br /> | |ID-Field not found -------------------------' | | | ||<br /> | |Media change requested -----------------------' | | ||<br /> | |Command aborted --------------------------------' | ||<br /> | |Track 0 not found --------------------------------' ||<br /> | |DAM not found --------------------------------------'|<br /> $F00005|byte |Write Precompensation |W<br /> $F00009|byte |Sector Count Register |W<br /> $F0000D|byte |Sector Number Register |W<br /> $F00011|byte |Cylinder Low Register BIT 7 6 5 4 3 2 1 0|W<br /> $F00015|byte |Cylinder High Register BIT 1 0|W<br /> $F00019|byte |Drive Head Register BIT 7 6 5 4 3 2 1 0|W<br /> | |Sector size (512 bytes, fixed) -------+ + + | | | | ||<br /> | |Drive (0 - Master, 1 - Slave) --------------' | | | ||<br /> | |Head number ----------------------------------+ + + +|<br /> $F0001D|byte |Status Register BIT 7 6 5 4 3 2 1 0|R<br /> | |Drive busy with executing Command ----' | | | | | | ||<br /> | |Drive Ready ----------------------------' | | | | | ||<br /> | |Drive Write Fault ------------------------' | | | | ||<br /> | |Drive Seek Complete ------------------------' | | | ||<br /> | |Data Request ---------------------------------' | | ||<br /> | |Corrected Data ---------------------------------' | ||<br /> | |Index pulse --------------------------------------' ||<br /> | |Error ----------------------------------------------'|<br /> $F0001D|byte |Command Register |W<br /> $F00039|byte |Alternate Status Register |R<br /> | |2nd status register, like 1st no deletion of the IRQ | |<br /> $F00039|byte |Data Output Register BIT 2 1 .|W<br /> | |Software Reset (1 - on)-------------------------+ | |<br /> | |Interrupt after end of Command (0 - on) ----------+ |<br /> $F0003D|byte |Active address BIT 6 5 4 3 2 1 0|R<br /> | |Drive is writing (0 - on) --------------' | | | | | ||<br /> | |Negated number of head number ------------+ + + + | ||<br /> | |Slave Drive Select (0 - on) ----------------------' ||<br /> | |Master Drive Select (0 - on) -----------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############OS ROMs ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FC0000|byte |TOS 192k ROMs |R<br /> : | : | : : : |:<br /> $FEFFFF|byte |TOS 192k ROMs |R<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############ST MMU Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8001|byte |MMU memory configuration BIT 3 2 1 0|R/W<br /> | |Bank 0 | | | ||<br /> | |00 - 128k ------------------------------------+-+ | ||<br /> | |01 - 512k ------------------------------------+-+ | ||<br /> | |10 - 2m --------------------------------------+-+ | ||<br /> | |11 - reserved --------------------------------+-' | ||<br /> | |Bank 1 | ||<br /> | |00 - 128k ----------------------------------------+-+|<br /> | |01 - 512k ----------------------------------------+-+|<br /> | |10 - 2m ------------------------------------------+-+|<br /> | |11 - reserved ------------------------------------+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon030 Processor Control ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8007|byte |Falcon Bus Control BIT 6 5 . 3 2 . 0|R/W (F030)<br /> | |RESET behavior -------------------------+ | | | ||<br /> | | 0 = always cold start ----------------+ | | | ||<br /> | | 1 = normal, &quot;memvalid&quot; is observed ---+ | | | ||<br /> | |STe Bus Emulation ------------------------' | | ||<br /> | | 0 = STE --------------------------------' | | ||<br /> | | 1 = Falcon -----------------------------' | | ||<br /> | |Blitter flag ---------------------------------' | ||<br /> | | 0 = BLiTTER On -----------------------------' | ||<br /> | | 1 = BLiTTER Off ----------------------------' | ||<br /> | |Blitter clock-----------------------------------' ||<br /> | | 0 - 8mhz, ------------------------------------' ||<br /> | | 1 - 16mhz ------------------------------------' ||<br /> | |68030 clock ----------------------------------------'|<br /> | | 0 - 8mhz -----------------------------------------'|<br /> | | 1 - 16mhz ----------------------------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############SHIFTER Video Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8201|byte |Video screen memory position (High byte) |R/W<br /> $FF8203|byte |Video screen memory position (Mid byte) |R/W<br /> $FF820D|byte |Video screen memory position (Low byte) |R/W (STe)<br /> $FF8205|byte |Video address pointer (High byte) |R<br /> $FF8207|byte |Video address pointer (Mid byte) |R<br /> $FF8209|byte |Video address pointer (Low byte) |R<br /> $FF820E|word |Offset to next line |R/W (F030)<br /> $FF820F|byte |Width of a scanline (width in words-1) |R/W (STe)<br /> $FF8210|word |Width of a scanline (width in words) |R/W (F030)<br /> $FF8264|byte |Horizontal scroll register without prefetch (0-15) |R/W (STe)<br /> $FF8265|byte |Horizontal scroll register with prefetch (0-15) |R/W (STe)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF820A|byte |Video synchronization mode BIT 1 0|R/W<br /> | |0 - 60hz, 1 - 50hz -------------------------------+ ||<br /> | |0 - internal, 1 - external sync ------------------' || (TT)<br /> | |0 - internal, 1 - external sync --------------------'| (!TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> | | BIT 11111198 76543210|<br /> | | 543210 |<br /> | | ST color value .....RRr .GGr.BBb|<br /> | | STe color value ....rRRR gGGGbBBB|<br /> $FF8240|word |Video palette register 0 Lowercase = LSB|R/W<br /> : | : | : : : : | :<br /> $FF825E|word |Video palette register 15 |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8260|byte |Shifter resolution BIT 1 0|R/W<br /> | |00 320x200x4 bitplanes (16 colors) ---------------+-+|<br /> | |01 640x200x2 bitplanes (4 colors) ----------------+-+|<br /> | |10 640x400x1 bitplane (1 colors) ----------------+-'|<br /> $FF8262|word |TT Shifter resolution BIT 15 . . 12|R/W (TT)<br /> | |Sample/Hold mode ----------------------------' ||<br /> | |Hypermono mode -------------------------------------'|<br /> | |Video Mode BIT 10 9 8|<br /> | |000 320x200x4 bitplanes (16 colors) -----------+-+-+|<br /> | |001 640x200x2 bitplanes (4 colors) ------------+-+-+|<br /> | |010 640x400x1 bitplane (2 colors)(Duochrome) -+-+-+|<br /> | |100 640x480x4 bitplanes (16 colors) -----------+-+-+|<br /> | |110 1280x960x1 bitplane (2 colors) ------------+-+-+|<br /> | |111 320x480x8 bitplanes (256 colors) ----------+-+-'|<br /> | |ST Palette Bank BIT 3 2 1 0|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF827E|word |STACY Display Driver BIT 10 9|R/W(STACY)<br /> | |Backlight on/off ---------------------------------+ ||<br /> | |Display on/off -------------------------------------+| <br /> -------+-----+-----------------------------------------------------+----------<br /> | | BIT 11111198 76543210|<br /> | | 543210 |<br /> | | TT color value ....RRRr GGGgBBBb|<br /> $FF8400|word |TT Palette 0 Lowercase = LSB|R/W (TT)<br /> : | : | : : : | : :<br /> $FF85FE|word |TT Palette 255 |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon030 VIDEL Video Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8006|byte |Monitor Type BIT 7 6 5 4 3 2 1 0|R (F030)<br /> | |Monitor Type (M0,M1) -----------------+-+ | | | | | ||<br /> | |00 - Monochrome (SM124) --------------+-+ | | | | | ||<br /> | |01 - RGB (SC1224) --------------------+-+ | | | | | ||<br /> | |10 - VGA Color -----------------------+-+ | | | | | ||<br /> | |11 - Television ----------------------+-+ | | | | | ||<br /> | |ST-RAM size ------------------------------+-+ | | | ||<br /> | | 00 = 1MB -------------------------------+-+ | | | ||<br /> | | 01 = 4MB -------------------------------+-+ | | | ||<br /> | | 10 = 16MB ------------------------------+-+ | | | ||<br /> | |ROM Wait Status ------------------------------+ + | ||<br /> | | 00 = Reserved ------------------------------+ + | ||<br /> | | 01 = 2 Wait (default) ----------------------+ + | ||<br /> | | 10 = 1 Wait --------------------------------+ + | ||<br /> | | 11 = 0 Wait --------------------------------+ + | ||<br /> | |Video bus width ----------------------------------+ ||<br /> | | 0 = 16 Bit, -----------------------------------+ ||<br /> | | 1 = 32 Bit (default) ---------------------------+ ||<br /> | |RAM Wait Status ------------------------------------+|<br /> | | 0 = 1 Wait (default) ----------------------------+|<br /> | | 1 = 0 Wait --------------------------------------+|<br /> $FF820E|word |Offset to next line |R/W (F030)<br /> $FF8210|word |VWRAP - Linewidth in words |R/W (F030)<br /> $FF8266|word |SPSHIFT BIT 10 9 8 . 6 5 4 3 2 1 0|R/W (F030)<br /> | |2-colour mode ------------------' | | | | | | | | ||<br /> | |Overlay mode ---------------------' | | | | | | | ||<br /> | |Truecolour mode --------------------' | | | | | | ||<br /> | |Use external Hsync (1 - on) ------------' | | | | | ||<br /> | |Use external Vsync (1 - on) --------------' | | | | ||<br /> | |8 Bitplane mode ----------------------------' | | | ||<br /> | |Color Palette Bank from 256 colors (0-15) ----+-+-+-+|<br /> | +-----------------------------------------------------+<br /> | | Horizontal Control Registers (BIT 9-0)|<br /> $FF8280|word |HHC - Horizontal Hold Counter |R (F030)<br /> $FF8282|word |HHT - Horizontal Hold Timer |R/W (F030)<br /> $FF8284|word |HBB - Horizontal Border Begin |R/W (F030)<br /> $FF8286|word |HBE - Horizontal Border End |R/W (F030)<br /> $FF8288|word |HDB - Horizontal Display Begin |R/W (F030)<br /> $FF828A|word |HDE - Horizontal Display End |R/W (F030)<br /> $FF828C|word |HSS - Horizontal SS |R/W (F030)<br /> $FF828E|word |HFS - Horizontal FS |R/W (F030)<br /> $FF8290|word |HEE - Horizontal EE |R/W (F030)<br /> | +-----------------------------------------------------+<br /> | | Vertical Control Registers (BIT 10-0)| <br /> $FF82A0|word |VFC - Vertcial Frequency Counter |R (F030)<br /> $FF82A2|word |VFT - Vertical Frequency Timer |R/W (F030)<br /> $FF82A4|word |VBB - Vertical Border Begin (count in 1/2 lines)|R/W (F030)<br /> $FF82A6|word |VBE - Vertical Border End (count in 1/2 lines)|R/W (F030)<br /> $FF82A8|word |VDB - Vertical Display Begin |R/W (F030)<br /> $FF82AA|word |VDE - Vertical Display End |R/W (F030)<br /> $FF82AC|word |VSS - Vertical SS |R/W (F030)<br /> | +-----------------------------------------------------+<br /> $FF82C0|word |Video Control (VCO) (Super78 puts $182 here) |R/W (F030)<br /> | | BIT 8 7 6 5 . 3 2 1 0|<br /> | |Hz base offset ---------------------' | | | | | | ||<br /> | | 0: 128 cycles --------------------' | | | | | | ||<br /> | | (ST Low/Mid on RGB | | | | | | ||<br /> | | and ST Hi on SM124) | | | | | | ||<br /> | | 1: 64 cycles (all the others) ---' | | | | | | ||<br /> | |Videobus width -----------------------' | | | | | ||<br /> | | 0: 16 Bit-Videobus -----------------' | | | | | ||<br /> | | 1: 32 Bit-Videobus (Falcon) --------' | | | | | ||<br /> | |HSync-Impulse --------------------------' | | | | ||<br /> | | 0: negative HSync-Impulse (5V &gt; 0V) --' | | | | ||<br /> | | 1: positive HSync-Impulse (0V &gt; 5V) --' | | | | ||<br /> | |VSync-Impulse ----------------------------' | | | ||<br /> | | 0: negative VSync-Impulse (5V &gt; 0V) ----' | | | ||<br /> | | 1: positive VSync-Impulse (0V &gt; 5V) ----' | | | ||<br /> | |Half-line-HSyncs------------------------------' | | ||<br /> | | 0: No Half-line-HSyncs ---------------------' | | ||<br /> | | 1: 15 Half-line-HSyncs from start of -------' | | ||<br /> | |Video base clock -------------------------------' | ||<br /> | | 0: Video base clock 32 MHz -------------------' | ||<br /> | | 1: Video base clock 25.175 MHz ---------------' | ||<br /> | |Monitor Type (M0,M1 same as bit 7&amp;6 in $FF0006) --+-+|<br /> | | 00 - Monochrome (SM124) ------------------------+-+|<br /> | | 01 - RGB (SC1224) ------------------------------+-+|<br /> | | 10 - VGA Color ---------------------------------+-+|<br /> | | 11 - Television --------------------------------+-+|<br /> $FF82C2|word |VCO - Video Control BIT 3 2 1 0|R/W (F030)<br /> | |Pixel width ----------------------------------+-+ | ||<br /> | | 00: 4 cycles/pixel -------------------------+-+ | ||<br /> | | 01: 2 cycles/pixel -------------------------+-+ | ||<br /> | | 10: 1 cycle/pixel -------------------------+-+ | ||<br /> | | 11: n/a -------------------------+-+ | ||<br /> | |Skip line (interlace) (1-on) ---------------------' ||<br /> | |Double lines (1-on) --------------------------------'| <br /> -------+-----+-----------------------------------------------------+----------<br /> ##############DMA/WD1772 Disk controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8600| |Reserved |<br /> $FF8602| |Reserved |<br /> $FF8604|word |FDC access/sector count |R/W<br /> $FF8606|word |DMA mode/status BIT 2 1 0|R<br /> | |Condition of FDC DATA REQUEST signal -----------' | ||<br /> | |0 - sector count null,1 - not null ---------------' ||<br /> | |0 - no error, 1 - DMA error ------------------------'|<br /> $FF8606|word |DMA mode/status BIT 8 7 6 . 4 3 2 1 .|W<br /> | |0 - read FDC/HDC,1 - write ---------' | | | | | | | |<br /> | |0 - HDC access,1 - FDC access --------' | | | | | | |<br /> | |0 - DMA on,1 - no DMA ------------------' | | | | | |<br /> | |Reserved ---------------------------------' | | | | |<br /> | |0 - FDC reg,1 - sector count reg -----------' | | | |<br /> | |0 - FDC access,1 - HDC access ----------------' | | |<br /> | |0 - pin A1 low, 1 - pin A1 high ----------------' | |<br /> | |0 - pin A0 low, 1 - pin A0 high ------------------' |<br /> $FF8609|byte |DMA base and counter (High byte) |R/W<br /> $FF860B|byte |DMA base and counter (Mid byte) |R/W<br /> $FF860D|byte |DMA base and counter (Low byte) |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############TT-SCSI DMA Controller ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8701|byte |DMA Address Pointer (Highest byte) |R/W (TT)<br /> $FF8703|byte |DMA Address Pointer (High byte) |R/W (TT)<br /> $FF8705|byte |DMA Address Pointer (Low byte) |R/W (TT)<br /> $FF8707|byte |DMA Address Pointer (Lowest byte) |R/W (TT)<br /> $FF8709|byte |DMA Byte Count (Highest byte) |R/W (TT)<br /> $FF870B|byte |DMA Byte Count (High byte) |R/W (TT)<br /> $FF870D|byte |DMA Byte Count (Low byte) |R/W (TT)<br /> $FF870F|byte |DMA Byte Count (Lowest byte) |R/W (TT)<br /> $FF8710|word |Residue Data Register (High Word) |R (TT)<br /> $FF8712|word |Residue Data Register (Low Word) |R (TT)<br /> $FF8715|byte |Control register BIT 7 6 . . . . 1 0|R/W (TT)<br /> | |Bus error ----------------------------' | | ||<br /> | |Byte count zero ------------------------' | ||<br /> | |Enable -------------------------------------------' ||<br /> | |DMA Direction (1 - out to port) --------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############TT-SCSI Drive Controller NCR 5380 ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8781|byte |Data register |R/W (TT)<br /> $FF8783|byte |Init-Command Register |R/W (TT)<br /> $FF8785|byte |Mode Register |R/W (TT)<br /> $FF8787|byte |Target-Command Register |R/W (TT)<br /> $FF8789|byte |ID Select/SCSI Control Register |R/W (TT)<br /> $FF878B|byte |Status Register |R/W (TT)<br /> $FF878D|byte |Target Receive/Input Data |R/W (TT)<br /> $FF878F|byte |Initiate Receive/Reset |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############YM2149 Sound Chip ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8800|byte |Read data/Register select |R/W<br /> | |0 Channel A Freq Low BIT 7 6 5 4 3 2 1 0|<br /> | |1 Channel A Freq High BIT 3 2 1 0|<br /> | |2 Channel B Freq Low BIT 7 6 5 4 3 2 1 0|<br /> | |3 Channel B Freq High BIT 3 2 1 0|<br /> | |4 Channel C Freq Low BIT 7 6 5 4 3 2 1 0|<br /> | |5 Channel C Freq High BIT 3 2 1 0|<br /> | |6 Noise Freq BIT 5 4 3 2 1 0|<br /> | |7 Mixer Control BIT 7 6 5 4 3 2 1 0|<br /> | | Port B IN/OUT (1=Output) -----------' | | | | | | ||<br /> | | Port A IN/OUT ------------------------' | | | | | ||<br /> | | Channel C Noise (1=Off) ----------------' | | | | ||<br /> | | Channel B Noise --------------------------' | | | ||<br /> | | Channel A Noise ----------------------------' | | ||<br /> | | Channel C Tone (0=On) ------------------------' | ||<br /> | | Channel B Tone ---------------------------------' ||<br /> | | Channel A Tone -----------------------------------'|<br /> | |8 Channel A Amplitude Control BIT 4 3 2 1 0|<br /> | | Fixed/Variable Level (0=Fixed) -----------' | | | ||<br /> | | Amplitude level control --------------------+-+-+-'|<br /> | |9 Channel B Amplitude Control BIT 4 3 2 1 0|<br /> | | Fixed/Variable Level ---------------------' | | | ||<br /> | | Amplitude level control --------------------+-+-+-'|<br /> | |10 Channel C Amplitude Control BIT 4 3 2 1 0|<br /> | | Fixed/Variable Level ---------------------' | | | ||<br /> | | Amplitude level control --------------------+-+-+-'|<br /> | |11 Envelope Period High BIT 7 6 5 4 3 2 1 0|<br /> | |12 Envelope Period Low BIT 7 6 5 4 3 2 1 0|<br /> | |13 Envelope Shape BIT 3 2 1 0|<br /> | | Continue -----------------------------------' | | ||<br /> | | Attack ---------------------------------------' | ||<br /> | | Alternate --------------------------------------' ||<br /> | | Hold ---------------------------------------------'|<br /> | | 00xx - \____________________________________ |<br /> | | 01xx - /|___________________________________ |<br /> | | 1000 - \|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\ |<br /> | | 1001 - \____________________________________ |<br /> | | 1010 - \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ |<br /> | | 1011 - \|----------------------------------- |<br /> | | 1100 - /|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/ |<br /> | | 1101 - /------------------------------------ |<br /> | | 1110 - /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ |<br /> | | 1111 - /|___________________________________ |<br /> | |14 Port A BIT 7 6 5 4 3 2 1 0|<br /> | | IDE Drive On/OFF -------------------+ | | | | | | || (F030)<br /> | | SCC A (0=LAN, 1=Serial2) -----------' | | | | | | || (TT)<br /> | | Monitor jack GPO pin -----------------+ | | | | | ||<br /> | | Internal Speaker On/Off --------------' | | | | | || (F030)<br /> | | Centronics strobe ----------------------' | | | | ||<br /> | | RS-232 DTR output ------------------------' | | | ||<br /> | | RS-232 RTS output --------------------------' | | ||<br /> | | Drive select 1 -------------------------------' | ||<br /> | | Drive select 0 ---------------------------------' ||<br /> | | Drive side select --------------------------------'|<br /> | |15 Port B (Parallel port) |<br /> $FF8802|byte |Write data |W<br /> | +-----------------------------------------------------+<br /> | |Note: PSG Registers are now fixed at these addresses.|<br /> | |All other addresses are masked out on the Falcon. Any|<br /> | |writes to the shadow registers $8804-$88FF will cause|<br /> | |bus errors. Game/Demo coders beware! |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############DMA Sound System ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8900|byte |Buffer interrupts BIT 3 2 1 0|R/W (F030)<br /> | |TimerA-Int at end of record buffer -----------' | | ||<br /> | |TimerA-Int at end of replay buffer -------------' | ||<br /> | |MFP-15-Int (I7) at end of record buffer ----------' ||<br /> | |MFP-15-Int (I7) at end of replay buffer ------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8901|byte |DMA Control Register BIT 7 . 5 4 . . 1 0|R/W<br /> | |1 - select record register -----------+ | | | || (F030) <br /> | |0 - select replay register -----------' | | | || (F030)<br /> | |Loop record buffer -----------------------' | | || (F030)<br /> | |DMA Record on ------------------------------' | || (F030)<br /> | |Loop replay buffer -------------------------------' || (STe)<br /> | |DMA Replay on --------------------------------------'| (STe)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8903|byte |Frame start address (high byte) |R/W (STe)<br /> $FF8905|byte |Frame start address (mid byte) |R/W (STe)<br /> $FF8907|byte |Frame start address (low byte) |R/W (STe)<br /> $FF8909|byte |Frame address counter (high byte) |R (STe)<br /> $FF890B|byte |Frame address counter (mid byte) |R (STe)<br /> $FF890D|byte |Frame address counter (low byte) |R (STe)<br /> $FF890F|byte |Frame end address (high byte) |R/W (STe)<br /> $FF8911|byte |Frame end address (mid byte) |R/W (STe)<br /> $FF8913|byte |Frame end address (low byte) |R/W (STe)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8920|byte |DMA Track Control BIT 5 4 . . 1 0|R/W (F030)<br /> | |00 - Set DAC to Track 0 ------------------+-+ | ||<br /> | |01 - Set DAC to Track 1 ------------------+-+ | ||<br /> | |10 - Set DAC to Track 2 ------------------+-+ | ||<br /> | |11 - Set DAC to Track 3 ------------------+-' | ||<br /> | |00 - Play 1 Track --------------------------------+-+|<br /> | |01 - Play 2 Tracks -------------------------------+-+|<br /> | |10 - Play 3 Tracks -------------------------------+-+|<br /> | |11 - Play 4 Tracks -------------------------------+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8921|byte |Sound mode control BIT 7 6 . . . . 1 0|R/W (STe)<br /> | |0 - Stereo, 1 - Mono -----------------' | | ||<br /> | |0 - 8bit -------------------------------+ | ||<br /> | |1 - 16bit (F030 only) ------------------' | || (F030)<br /> | |Frequency control bits | ||<br /> | |00 - Off (F030 only) -----------------------------+-+| (F030)<br /> | |00 - 6258hz frequency (STe only) -----------------+-+|<br /> | |01 - 12517hz frequency ---------------------------+-+|<br /> | |10 - 25033hz frequency ---------------------------+-+|<br /> | |11 - 50066hz frequency ---------------------------+-'|<br /> | |Samples are always signed. In stereo mode, data is |<br /> | |arranged in pairs with high pair the left channel,low|<br /> | |pair right channel. Sample length MUST be even in |<br /> | |either mono or stereo mode. |<br /> | |Example: 8 bit Stereo : LRLRLRLRLRLRLRLR |<br /> | | 16 bit Stereo : LLRRLLRRLLRRLLRR (F030) |<br /> | |2 track 16 bit stereo : LLRRllrrLLRRllrr (F030) |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############STe Microwire Controller (STe/TT only!) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8922|byte |Microwire data register |R/W (Mwr)<br /> $FF8924|byte |Microwire mask register |R/W (Mwr)<br /> | +-----------------------------------------------------+<br /> | |!! ATTENTION !! Microwire is now obsolete! It is not |<br /> | |present in the Falcon030 and is unlikely to be in any|<br /> | |future machines. You have been warned. | <br /> | +-----------------------------------------------------+<br /> | |Volume/tone controller commands (Address %10)|<br /> | |Master Volume 10 011 DDDDDD|<br /> | |Left Volume 10 101 .DDDDD|<br /> | |Right Volume 10 100 .DDDDD|<br /> | |Treble 10 010 ..DDDD|<br /> | |Bass 10 001 ..DDDD|<br /> | |Mixer 10 000 ....DD|<br /> | +-----------------------------------------------------+<br /> | |Volume/tone controller values |<br /> | |Master Volume : 0-40 (0 = -80dB, 40 = 0dB) |<br /> | |Left/Right Volume : 0-20 (0 = -40dB, 20 = 0dB) |<br /> | |Treble/bass : 0-12 (0 = -12dB, 12 = +12dB) |<br /> | |Mixer : 0-3: |<br /> | | 0 = DMA only |<br /> | | 1 = DMA + YM2149 |<br /> | | 2 = DMA only |<br /> | | 3 = reserved |<br /> | | (there is no DMA + (YM2149 - 12dB) mode!) |<br /> | +-----------------------------------------------------+<br /> | |Procedure: Set mask register to $7ff. Read data |<br /> | |register and save original value.Write data register.|<br /> | |Compare data register with original value, repeat |<br /> | |until data register returns to original value to |<br /> | |ensure data has been sent over the interface. |<br /> | +-----------------------------------------------------+<br /> | |Interrupts: Timer A can be set to interrupt at the |<br /> | |end of a frame. Alternatively, the GPI7 (MFP mono |<br /> | |detect) can be used to generate interrupts thereby |<br /> | |freeing up Timer A. In this case, the active edge |<br /> | |$FFFA03 must be set by or-ing the active edge of |<br /> | |$FFFA03 with the contents of $FF8260: |<br /> | |$FF8260 - 2 (mono) or.b #$80 with edge |<br /> | |$FF8260 - 0,1 (colour) and.b #$7F with edge |<br /> | |This will generate an interrupt at the START of a |<br /> | |frame, instead of at the end as with Timer A. To |<br /> | |generate an interrupt at the END of a frame, simply |<br /> | |reverse the edge values. |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon030 DMA/DSP Controllers ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8930|word |Crossbar Source Controller |R/W (F030)<br /> | +-----------------------------------------------------+<br /> | |Source: A/D Convertor BIT 15 14 13 12|<br /> | |1 - Connect, 0 - disconnect ---------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock (Don't use) -----------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Source: External Input BIT 11 10 9 8|<br /> | |0 - DSP IN, 1 - All others ----------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock -----------------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Source: DSP-XMIT BIT 7 6 5 4|<br /> | |0 - Tristate and disconnect DSP -----------+ | | ||<br /> | | (Only for external SSI use) | | | ||<br /> | |1 - Connect DSP to multiplexer ------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock -----------------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Source: DMA-PLAYBACK BIT 3 2 1 0|<br /> | |0 - Handshaking on, dest DSP-REC ----------+ | | ||<br /> | |1 - Destination is not DSP-REC ------------' | | ||<br /> | |00 - 25.175Mhz clock -------------------------+--+ ||<br /> | |01 - External clock --------------------------+--+ ||<br /> | |10 - 32Mhz clock -----------------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8932|word |Crossbar Destination Controller |R/W (F030)<br /> | +-----------------------------------------------------+<br /> | |Destination: D/A Convertor BIT 15 14 13 12|<br /> | |1 - Connect, 0 - Disconnect ---------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Destination: External Output BIT 11 10 9 8|<br /> | |0 - DSP out, 1 - All others ---------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Destination: DSP-RECORD BIT 7 6 5 4|<br /> | |0 - Tristate and disconnect DSP -----------+ | | ||<br /> | | (Only for external SSI use) | | | ||<br /> | |1 - Connect DSP to multiplexer ------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> | +-----------------------------------------------------+<br /> | |Destination: DMA-RECORD BIT 3 2 1 0|<br /> | |0 - Handshaking on, src DSP-XMIT ----------+ | | ||<br /> | |1 - Source is not DSP-XMIT ----------------' | | ||<br /> | |00 - Source DMA-PLAYBACK ---------------------+--+ ||<br /> | |01 - Source DSP-XMIT -------------------------+--+ ||<br /> | |10 - Source External Input -------------------+--+ ||<br /> | |11 - Source A/D Convertor --------------------+--' ||<br /> | |0 - Handshake on, 1 - Handshake off ----------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8934|byte |Frequency Divider External Clock BIT 3 2 1 0|R/W (F030)<br /> | |0000 - STe-Compatible mode |<br /> | |0001 - 1111 Divide by 256 and then number |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8935|byte |Frequency Divider Internal Sync BIT 3 2 1 0|R/W (F030)<br /> | |0000 - STe-Compatible mode 1000 - 10927Hz* |<br /> | |0001 - 49170Hz 1001 - 9834Hz |<br /> | |0010 - 32780Hz 1010 - 8940Hz* |<br /> | |0011 - 24585Hz 1011 - 8195Hz |<br /> | |0100 - 19668Hz 1100 - 7565Hz* |<br /> | |0101 - 16390Hz 1101 - 7024Hz* |<br /> | |0110 - 14049Hz* 1110 - 6556Hz* |<br /> | |0111 - 12292Hz 1111 - 6146Hz* |<br /> | | * - Invalid for CODEC |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8936|byte |Record Tracks Select BIT 1 0|R/W (F030)<br /> | |00 - Record 1 Track ------------------------------+-+|<br /> | |01 - Record 2 Tracks -----------------------------+-+|<br /> | |10 - Record 3 Tracks -----------------------------+-+|<br /> | |11 - Record 4 Tracks -----------------------------+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8937|byte |CODEC Input Source from 16bit adder BIT 1 0|R/W (F030)<br /> | |Source: Multiplexer ------------------------------' ||<br /> | |Source: A/D Convertor ------------------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8938|byte |CODEC ADC-Input for L+R Channel BIT 1 0|R/W (F030)<br /> | |0 - Microphone, 1 - Soundchip L R|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8939|byte |Channel amplification BIT LLLL RRRR|R/W (F030)<br /> | | Amplification is in +1.5dB steps |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF893A|word |Channel attenuation BIT LLLL RRRR|R/W (F030)<br /> | | Attenuation is in -1.5dB steps |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF893C|byte |CODEC-Status BIT 1 0|R/W (F030)<br /> | |Left Channel Overflow ----------------------------' ||<br /> | |Right Channel Overflow -----------------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8941|byte |GPx Data Direction BIT 2 1 0|R/W (F030)<br /> | |0 - In, 1 - Out --------------------------------+-+-'|<br /> | | For the GP0-GP2 pins on the DSP connector |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8943|byte |GPx Data Port BIT 2 1 0|R/W (F030)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############TT Clock Chip (MC146818A @ 32.768 khz) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8961|byte |Register select |W (TT)<br /> | |0 - Current Second |<br /> | |1 - Second for alarm |<br /> | |2 - Current Minute |<br /> | |3 - Minute for alarm |<br /> | |4 - Current Hour |<br /> | |5 - Hour for alarm |<br /> | |6 - Day of week (1=Sunday, 2=Monday, 3=...) |<br /> | |7 - Day of Month |<br /> | |8 - Month |<br /> | |9 - Year (example : '93' for this year) |<br /> | |A BIT 7|<br /> | | If set, update time in progress ----------------'|<br /> | | don't read time &amp; date registers |<br /> | |B BIT 7 6 5 4 3 2 1 0|<br /> | |1 = Write Protect time &amp; date --------' | | | | ||<br /> | |1 = Enable alarm interrupt ---------------' | | | ||<br /> | |1 = Interrupt after time updated -----------' | | ||<br /> | |1 = Format Binary, 0 = Format BCD --------------' | ||<br /> | |1 = 24hr format, 0 = 12hr format -----------------' ||<br /> | |1 = Summer hours, 0 = Winter hours -----------------'|<br /> | |C BIT 6 5 4|<br /> | | ??? -------------------------------------------' | ||<br /> | |1 = alarm is ringing -----------------------------' ||<br /> | |1 = date is updated --------------------------------'|<br /> | |On interrupt, read this register to determine source.|<br /> | |D BIT 7|<br /> | |1 = Battery dead -----------------------------------'|<br /> $FF8963|byte |Register data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Blitter (Not present on TT!) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8A00|word |Halftone-RAM, Word 0 |R/W (Blit)<br /> : | : | : : : : | : :<br /> $FF8A1E|word |Halftone-RAM, Word 15 |R/W (Blit)<br /> $FF8A20|word |Source X Increment (signed,even)|R/W (Blit)<br /> $FF8A22|word |Source Y Increment (signed,even)|R/W (Blit)<br /> $FF8A24|long |Source Address Register (24 bit,even)|R/W (Blit)<br /> $FF8A28|word |Endmask 1 (First write of a line)|R/W (Blit)<br /> $FF8A2A|word |Endmask 2 (All other line writes)|R/W (Blit)<br /> $FF8A2C|word |Endmask 3 (Last write of a line)|R/W (Blit)<br /> $FF8A2E|word |Destination X Increment (signed,even)|R/W (Blit)<br /> $FF8A30|word |Destination Y Increment (signed,even)|R/W (Blit)<br /> $FF8A32|long |Destination Address Register (24 bit,even)|R/W (Blit)<br /> $FF8A36|word |Words per Line in Bit-Block (0=65536)|R/W (Blit)<br /> $FF8A38|word |Lines per Bit-Block (0=65536)|R/W (Blit)<br /> $FF8A3A|byte |Halftone Operation Register BIT 1 0|R/W (Blit)<br /> | |00 - All ones ------------------------------------+-+|<br /> | |01 - Halftone ------------------------------------+-+|<br /> | |10 - Source --------------------------------------+-+|<br /> | |11 - Source AND Halftone -------------------------+-'|<br /> $FF8A3B|byte |Logical Operation Register BIT 3 2 1 0|R/W (Blit)<br /> | |0000 All zeros -------------------------------+-+-+-+|<br /> | |0001 Source AND destination ------------------+-+-+-+|<br /> | |0010 Source AND NOT destination --------------+-+-+-+|<br /> | |0011 Source ----------------------------------+-+-+-+|<br /> | |0100 NOT source AND destination --------------+-+-+-+|<br /> | |0101 Destination -----------------------------+-+-+-+|<br /> | |0110 Source XOR destination ------------------+-+-+-+|<br /> | |0111 Source OR destination -------------------+-+-+-+|<br /> | |1000 NOT source AND NOT destination ----------+-+-+-+|<br /> | |1001 NOT source XOR destination --------------+-+-+-+|<br /> | |1010 NOT destination -------------------------+-+-+-+|<br /> | |1011 Source OR NOT destination ---------------+-+-+-+|<br /> | |1100 NOT source ------------------------------+-+-+-+|<br /> | |1101 NOT source OR destination ---------------+-+-+-+|<br /> | |1110 NOT source OR NOT destination -----------+-+-+-+|<br /> | |1111 All ones --------------------------------+-+-+-'|<br /> $FF8A3C|byte |Line Number Register BIT 7 6 5 . 3 2 1 0|R/W (Blit)<br /> | |BUSY ---------------------------------' | | | | | ||<br /> | |0 - Share bus, 1 - Hog bus -------------' | | | | ||<br /> | |SMUDGE mode ------------------------------' | | | ||<br /> | |Halftone line number -------------------------+-+-+-'|<br /> $FF8A3D|byte |SKEW Register BIT 7 6 . . 3 2 1 0|R/W (Blit)<br /> | |Force eXtra Source Read --------------' | | | | ||<br /> | |No Final Source Read -------------------' | | | ||<br /> | |Source skew ----------------------------------+-+-+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############SCC-DMA (TT Only!) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8C01|byte |DMA Address Pointer (Highest Byte) |R/W (TT)<br /> $FF8C03|byte |DMA Address Pointer (High Byte) |R/W (TT)<br /> $FF8C05|byte |DMA Address Pointer (Low Byte) |R/W (TT)<br /> $FF8C07|byte |DMA Address Pointer (Lowest Byte) |R/W (TT)<br /> $FF8C09|byte |DMA Byte Count (Highest-Byte) |R/W (TT)<br /> $FF8C0B|byte |DMA Byte Count (High-Byte) |R/W (TT)<br /> $FF8C0D|byte |DMA Byte Count (Low-Byte) |R/W (TT)<br /> $FF8C0F|byte |DMA Byte Count (Lowest-Byte) |R/W (TT)<br /> $FF8C10|word |Residue Data Register (High-Word) |R (TT)<br /> $FF8C12|word |Residue Data register (Low-Word) |R (TT)<br /> $FF8C15|byte |Control register BIT 7 6 . . . . 1 0|R/W (TT)<br /> | |Bus error ----------------------------' | | ||<br /> | |Byte count zero ------------------------' | ||<br /> | |Enable -------------------------------------------' ||<br /> | |DMA Direction (1 - out to port) --------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Zilog 8530 SCC (MSTe/TT/F030) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8C81|byte |Channel A - Control Register |R/W (SCC)<br /> $FF8C83|byte |Channel A - Data Register |R/W (SCC)<br /> $FF8C85|byte |Channel B - Control Register |R/W (SCC)<br /> $FF8C87|byte |Channel B - Data Register |R/W (SCC)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############VME Bus System Control Unit (MSTe/TT) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E01|byte |VME sys_mask BIT 7 6 5 4 . 2 1 .|R/W (VME)<br /> $FF8E03|byte |VME sys_stat BIT 7 6 5 4 . 2 1 .|R (VME)<br /> | |_SYSFAIL in VMEBUS -------------------' | | | | | |program<br /> | |MFP ------------------------------------' | | | | |autovec<br /> | |SCC --------------------------------------' | | | |autovec<br /> | |VSYNC --------------------------------------' | | |program<br /> | |HSYNC ------------------------------------------' | |program<br /> | |System software INT ------------------------------' |program<br /> | +-----------------------------------------------------+<br /> | |Reading sys_mask resets pending int-bits in sys_stat,|<br /> | |so read sys_stat first. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E05|byte |VME sys_int BIT 0|R/W (VME)<br /> | |Setting bit 0 to 1 forces an INT of level 1. INT must|Vector $64<br /> | |be enabled in sys_mask to use it. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E0D|byte |VME vme_mask BIT 7 6 5 4 3 2 1 .|R/W (VME)<br /> $FF8E0F|byte |VME vme_stat BIT 7 6 5 4 3 2 1 .|R (VME)<br /> | |_IRQ7 from VMEBUS --------------------' | | | | | | |program<br /> | |_IRQ6 from VMEBUS/MFP ------------------' | | | | | |program<br /> | |_IRQ5 from VMEBUS/SCC --------------------' | | | | |program<br /> | |_IRQ4 from VMEBUS --------------------------' | | | |program<br /> | |_IRQ3 from VMEBUS/soft -----------------------' | | |prog/autov<br /> | |_IRQ2 from VMEBUS ------------------------------' | |program<br /> | |_IRQ1 from VMEBUS --------------------------------' |program<br /> | +-----------------------------------------------------+<br /> | |MFP-int and SCC-int are hardwired to the VME-BUS-ints|<br /> | |(or'ed). Reading vme_mask resets pending int-bits in |<br /> | |vme_stat, so read vme_stat first. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E07|byte |VME vme_int BIT 0|R/W (TT)<br /> | |Setting bit 0 to 1 forces an INT of level 3. INT must|Vector $6C<br /> | |be enabled in vme_mask to use it. |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E09|byte |General purpose register - does nothing |R/W (TT)<br /> $FF8E0B|byte |General purpose register - does nothing |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Mega STe Cache/Processor Control ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF8E21|byte |Mega STe Cache/Processor Control BIT 15-1 0|R/W (MSTe)<br /> | |Cache enable lines (set all to 1 to enable) -----' ||<br /> | |CPU Speed (0 - 8mhz, 1 - 16mhz) --------------------'|<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############DIP Switches (MSTe/TT) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF9200|byte |DIP Switches (MSTe/TT) BIT 7 6 5 4 3 2 1 0|R (MSTe/TT)<br /> | |Sound DMA active ---------------------' | ||<br /> | |Floppy Drive 1.44 HD active ------------' ||<br /> | |CaTTamaran installed -------------------------------'|<br /> | | |<br /> | |That register is mirrored by the OS in &quot;_SWI&quot; Cookie |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############STe/F030 Extended Joystick/Lightpen Ports ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FF9200|word |Fire buttons 1-4 Bit 3 2 1 0|R (Ext)<br /> | |Pause/F0 -------------------------------------' | | ||<br /> | |F1 ---------------------------------------------' | ||<br /> | |F2 -----------------------------------------------' ||<br /> | |Option/F3 ------------------------------------------'|<br /> $FF9202|word |Read Mask (0 - pin read) |W (Ext)<br /> $FF9202|word |Joystick Inputs BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> | |Controller 1 pin 4 -------------------' | | | | | | ||<br /> | |Controller 1 pin 3 ---------------------' | | | | | ||<br /> | |Controller 1 pin 2 -----------------------' | | | | ||<br /> | |Controller 1 pin 1 -------------------------' | | | ||<br /> | |Controller 0 pin 4 ---------------------------' | | ||<br /> | |Controller 0 pin 3/Paddle 1 Trigger ------------' | ||<br /> | |Controller 0 pin 2/Paddle 0 Trigger --------------' ||<br /> | |Controller 0 pin 1 ---------------------------------'|<br /> | | BIT 15 14 13 12 11 10 9 8|<br /> | |Controller 1 pin 14 ------------' | | | | | | ||<br /> | |Controller 1 pin 13 ----------------' | | | | | ||<br /> | |Controller 1 pin 12 -------------------' | | | | ||<br /> | |Controller 1 pin 11 ----------------------' | | | ||<br /> | |Controller 0 pin 14 -------------------------' | | ||<br /> | |Controller 0 pin 13 ----------------------------' | ||<br /> | |Controller 0 pin 12 ------------------------------' ||<br /> | |Controller 0 pin 11 --------------------------------'|<br /> $FF9210|word |X Paddle 0 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9212|word |Y Paddle 0 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9214|word |X Paddle 1 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9216|word |Y Paddle 1 Position BIT 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9220|word |Lightpen X-Position BIT 9 8 7 6 5 4 3 2 1 0|R (Ext)<br /> $FF9222|word |Lightpen Y-Position BIT 9 8 7 6 5 4 3 2 1 0|R (Ext)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon VIDEL Palette Registers ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> | | BIT 33222222 22221111 11111198 76543210|<br /> | | 10987654 32109876 543210 |<br /> | | RRRRRr.. GGGGGg.. ........ BBBBBb..|<br /> $FF9800|long |Palette Register 0 Lowercase = LSB|R/W (F030)<br /> : | : | : : : | : :<br /> $FF98FC|long |Palette Register 255 |R/W (F030)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Falcon DSP Host Interface ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFA200|byte |Interrupt Ctrl Register BIT 7 6 5 4 3 . 1 0|R/W (F030)<br /> X:$FFE9| |INIT bit -----------------------------' | | | | | ||<br /> | |00 - Interupt mode (DMA off) -----------+-+ | | | ||<br /> | |01 - 24-bit DMA mode -------------------+-+ | | | ||<br /> | |10 - 16-bit DMA mode -------------------+-+ | | | ||<br /> | |11 - 8-bit DMA mode --------------------+-' | | | ||<br /> | |Host Flag 1 --------------------------------' | | ||<br /> | |Host Flag 0 ----------------------------------' | ||<br /> | | Host mode Data transfers: | ||<br /> | | Interrupt mode | ||<br /> | |00 - No interrupts (Polling) ---------------------+-+|<br /> | |01 - RXDF Request (Interrupt) --------------------+-+|<br /> | |10 - TXDE Request (Interrupt) --------------------+-+|<br /> | |11 - RXDF and TXDE Request (Interrupts) ----------+-+|<br /> | | DMA Mode | ||<br /> | |00 - No DMA --------------------------------------+-+|<br /> | |01 - DSP to Host Request (RX) --------------------+-+|<br /> | |10 - Host to DSP Request (TX) --------------------+-+|<br /> | |11 - Undefined (Illegal) -------------------------+-'|<br /> $FFA201|byte |Command Vector Register BIT 7 . . 4 3 2 1 0|R/W (F030)<br /> X:$FFE9| |Host Command Bit (Handshake)----------' | | | | ||<br /> | |Host Vector (0-31) -------------------------+-+-+-+-'|<br /> $FFA202|byte |Interrupt Status Reg BIT 7 6 . 4 3 2 1 0|R (F030)<br /> X:$FFE8| |ISR Host Request ---------------------' | | | | | ||<br /> | |ISR DMA Status -------------------------' | | | | ||<br /> | |Host Flag 3 --------------------------------' | | | ||<br /> | |Host Flag 2 ----------------------------------' | | ||<br /> | |ISR Transmitter Ready (TRDY) -------------------' | ||<br /> | |ISR Transmit Data Register Empty (TXDE) ----------' ||<br /> | |ISR Receive Data Register Full (RXDF) --------------'|<br /> $FFA203|byte |Interrupt Vector Register |R/W (F030)<br /> $FFA204|byte |Unused | (F030)<br /> $FFA205|byte |DSP-Word High |R/W (F030)<br /> X:$FFEB| | |<br /> $FFA206|byte |DSP-Word Mid |R/W (F030)<br /> X:$FFEB| | |<br /> $FFA207|byte |DSP-Word Low |R/W (F030)<br /> X:$FFEB| | |<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############MFP 68901 - Multi Function Peripheral Chip ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> | | MFP Master Clock is 2,457,600 cycles/second |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA01|byte |Parallel Port Data Register |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA03|byte |Active Edge Register BIT 7 6 5 4 . 2 1 0|R/W<br /> | |Monochrome monitor detect ------------' | | | | | | ||<br /> | |RS-232 Ring indicator ------------------' | | | | | ||<br /> | |FDC/HDC interrupt ------------------------' | | | | ||<br /> | |Keyboard/MIDI interrupt --------------------' | | | ||<br /> | |Reserved -------------------------------------' | | ||<br /> | |RS-232 CTS (input) -----------------------------' | ||<br /> | |RS-232 DCD (input) -------------------------------' ||<br /> | |Centronics busy ------------------------------------'|<br /> | +-----------------------------------------------------+<br /> | | When port bits are used for input only: |<br /> | |0 - Interrupt on pin high-low conversion |<br /> | |1 - Interrupt on pin low-high conversion |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA05|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W<br /> | |0 - In, 1 - Out ----------------------+-+-+-+-+-+-+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA07|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA0B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA0F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA13|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W<br /> | |MFP Address | | | | | | | ||<br /> | |$13C GPI7-Monochrome Detect ----------' | | | | | | ||<br /> | |$138 RS-232 Ring Detector ------------' | | | | | ||<br /> | |$134 (STe sound) Timer A --------------' | | | | ||<br /> | |$130 Receive buffer full ----------------' | | | ||<br /> | |$12C Receive error ------------------' | | ||<br /> | |$128 Send buffer empty --------------------' | ||<br /> | |$124 Send error ----------------------' ||<br /> | |$120 (HBL) Timer B ------------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA09|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA0D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA11|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W<br /> $FFFA15|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W<br /> | |MFP Address | | | | | | | ||<br /> | |$11C FDC/HDC ----------' | | | | | | ||<br /> | |$118 Keyboard/MIDI ------------' | | | | | ||<br /> | |$114 (200hz clock) Timer C --------------' | | | | ||<br /> | |$110 (USART timer) Timer D ----------------' | | | ||<br /> | |$10C Blitter done ------------------' | | ||<br /> | |$108 RS-232 CTS - input --------------------' | ||<br /> | |$104 RS-232 DCD - input ----------------------' ||<br /> | |$100 Centronics Busy ------------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA17|byte |Vector Register BIT 7 6 5 4 3 . . .|R/W<br /> | |Vector Base Offset -------------------+-+-+-' | |<br /> | |1 - *Software End-interrupt mode -------------+ |<br /> | |0 - Automatic End-interrupt mode -------------' |<br /> | |* - Default operating mode |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA19|byte |Timer A Control BIT 4 3 2 1 0|R/W<br /> $FFFA1B|byte |Timer B Control BIT 4 3 2 1 0|R/W<br /> | |Reset (force output low) -------------------' | | | ||<br /> | +----------------------------------------------+-+-+-++<br /> | |0000 - Timer stop, no function executed |<br /> | |0001 - Delay mode, divide by 4 |<br /> | |0010 - : : 10 |<br /> | |0011 - : : 16 |<br /> | |0100 - : : 50 |<br /> | |0101 - : : 64 |<br /> | |0110 - : : 100 |<br /> | |0111 - Delay mode, divide by 200 |<br /> | |1000 - Event count mode |<br /> | |1xxx - Pulse extension mode, divide as above |<br /> | +-----------------------------------------------------+<br /> $FFFA1F|byte |Timer A Data |R/W<br /> $FFFA21|byte |Timer B Data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA1D|byte |Timer C &amp; D Control BIT 6 5 4 . 2 1 0|R/W<br /> | | Timer Timer|<br /> | | C D |<br /> | +-----------------------------------------------------+<br /> | |000 - Timer stop |<br /> | |001 - Delay mode, divide by 4 |<br /> | |010 - : : 10 |<br /> | |011 - : : 16 |<br /> | |100 - : : 50 |<br /> | |101 - : : 64 |<br /> | |110 - : : 100 |<br /> | |111 - Delay mode, divide by 200 |<br /> | +-----------------------------------------------------+<br /> $FFFA23|byte |Timer C Data |R/W<br /> $FFFA25|byte |Timer D Data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA27|byte |Sync Character |R/W<br /> $FFFA29|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W<br /> | |Clock divide (1 - div by 16) ---------' | | | | | | ||<br /> | |Word Length 00 - 8 bits ----------------+-+ | | | | ||<br /> | | 01 - 7 bits ----------------+-+ | | | | ||<br /> | | 10 - 6 bits ----------------+-+ | | | | ||<br /> | | 11 - 5 bits ----------------+-' | | | | ||<br /> | |Bits Stop Start Format | | | | ||<br /> | |00 0 0 Synchronous ----------------+-+ | | ||<br /> | |01 1 1 Asynchronous ---------------+-+ | | ||<br /> | |10 1 1.5 Asynchronous ---------------+-+ | | ||<br /> | |11 1 2 Asynchronous ---------------+-' | | ||<br /> | |Parity (0 - ignore parity bit) -----------------' | ||<br /> | |Parity (0 - odd parity,1 - even) -----------------' ||<br /> | |Unused ---------------------------------------------'|<br /> $FFFA2B|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W<br /> | |Buffer full --------------------------' | | | | | | ||<br /> | |Overrun error --------------------------' | | | | | ||<br /> | |Parity error -----------------------------' | | | | ||<br /> | |Frame error --------------------------------' | | | ||<br /> | |Found - Search/Break detected ----------------' | | ||<br /> | |Match/Character in progress --------------------' | ||<br /> | |Synchronous strip enable -------------------------' ||<br /> | |Receiver enable bit --------------------------------'|<br /> $FFFA2D|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W<br /> | |Buffer empty -------------------------' | | | | | | ||<br /> | |Underrun error -------------------------' | | | | | ||<br /> | |Auto turnaround --------------------------' | | | | ||<br /> | |End of transmission ------------------------' | | | ||<br /> | |Break ----------------------------------------' | | ||<br /> | |High bit ---------------------------------------' | ||<br /> | |Low bit ------------------------------------------' ||<br /> | |Transmitter enable ---------------------------------'|<br /> $FFFA2F|byte |USART data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Floating Point Coprocessor (CIR Interface in MSTe) ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA40|word |FP_Stat Response-Register |??? (MSTe)<br /> $FFFA42|word |FP_Ctl Control-Register |??? (MSTe)<br /> $FFFA44|word |FP_Save Save-Register |??? (MSTe)<br /> $FFFA46|word |FP_Restor Restore-Register |??? (MSTe)<br /> $FFFA48|word | |??? (MSTe)<br /> $FFFA4A|word |FP_Cmd Command-Register |??? (MSTe)<br /> $FFFA4E|word |FP_Ccr Condition-Code-Register |??? (MSTe)<br /> $FFFA50|long |FP_Op Operand-Register |??? (MSTe)<br /> $FFFA54|word |FP_Selct Register Select |??? (MSTe)<br /> $FFFA58|long |FP_Iadr Instruction Address |??? (MSTe)<br /> $FFFA5C|long | Operand Address |??? (MSTe)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############MFP 68901 #2 (MFP2) - TT Only ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA81|byte |Parallel Port Data Register |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA83|byte |Active Edge Register BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | +-----------------------------------------------------+<br /> | | When port bits are used for input only: |<br /> | |0 - Interrupt on pin high-low conversion |<br /> | |1 - Interrupt on pin low-high conversion |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA85|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |0 - In, 1 - Out ----------------------+-+-+-+-+-+-+-'|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA87|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA8B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA8F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA93|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |MFP Address | | | | | | | ||<br /> | |$17C TT-SCSI NCR5380 ---------' | | | | | | ||<br /> | |$178 RTC (MC146818A) -----------' | | | | | ||<br /> | |$174 Timer A -------------' | | | | ||<br /> | |$170 Receive buffer full ---------------' | | | ||<br /> | |$16C Receive error -----------------' | | ||<br /> | |$168 Send buffer empty -------------------' | ||<br /> | |$164 Send error ---------------------' ||<br /> | |$160 Timer B -----------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA89|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA8D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA91|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> $FFFA95|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |MFP Address | | | | | | | ||<br /> | |$15C SCSI DMA Controller ---------' | | | | | | ||<br /> | |$158 (Reserved) GPIP 4 -----------' | | | | | ||<br /> | |$154 Timer C -------------' | | | | ||<br /> | |$150 Timer D ---------------' | | | ||<br /> | |$14C SCC B Ring Indicator -----------------' | | ||<br /> | |$148 SCC DMA Controller -------------------' | ||<br /> | |$144 General Purpose Input 1 ---------------------' ||<br /> | |$140 General Purpose Input 0 -----------------------'|<br /> | |1 - Enable Interrupt 0 - Disable Interrupt|<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA97|byte |Vector Register BIT 7 6 5 4 3 . . .|R/W (TT)<br /> | |Vector Base Offset -------------------+-+-+-' | |<br /> | |1 - *Software End-interrupt mode -------------+ |<br /> | |0 - Automatic End-interrupt mode -------------' |<br /> | |* - Default operating mode |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA99|byte |Timer A Control BIT 4 3 2 1 0|R/W (TT)<br /> $FFFA9B|byte |Timer B Control BIT 4 3 2 1 0|R/W (TT)<br /> | |Reset (force output low) -------------------' | | | ||<br /> | +----------------------------------------------+-+-+-++<br /> | |0000 - Timer stop, no function executed |<br /> | |0001 - Delay mode, divide by 4 |<br /> | |0010 - : : 10 |<br /> | |0011 - : : 16 |<br /> | |0100 - : : 50 |<br /> | |0101 - : : 64 |<br /> | |0110 - : : 100 |<br /> | |0111 - Delay mode, divide by 200 |<br /> | |1000 - Event count mode |<br /> | |1xxx - Pulse extension mode, divide as above |<br /> | +-----------------------------------------------------+<br /> $FFFA9F|byte |Timer A Data |R/W (TT)<br /> $FFFAA1|byte |Timer B Data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFA9D|byte |Timer C &amp; D Control BIT 6 5 4 . 2 1 0|R/W (TT)<br /> | | Timer Timer|<br /> | | C D |<br /> | +-----------------------------------------------------+<br /> | |000 - Timer stop |<br /> | |001 - Delay mode, divide by 4 |<br /> | |010 - : : 10 |<br /> | |011 - : : 16 |<br /> | |100 - : : 50 |<br /> | |101 - : : 64 |<br /> | |110 - : : 100 |<br /> | |111 - Delay mode, divide by 200 |<br /> | +-----------------------------------------------------+<br /> $FFFAA3|byte |Timer C Data |R/W (TT)<br /> $FFFAA5|byte |Timer D Data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFAA7|byte |Sync Character |R/W (TT)<br /> $FFFAA9|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W (TT)<br /> | |Clock divide (1 - div by 16) ---------' | | | | | | ||<br /> | |Word Length 00 - 8 bits ----------------+-+ | | | | ||<br /> | | 01 - 7 bits ----------------+-+ | | | | ||<br /> | | 10 - 6 bits ----------------+-+ | | | | ||<br /> | | 11 - 5 bits ----------------+-' | | | | ||<br /> | |Bits Stop Start Format | | | | ||<br /> | |00 0 0 Synchronous ----------------+-+ | | ||<br /> | |01 1 1 Asynchronous ---------------+-+ | | ||<br /> | |10 1 1.5 Asynchronous ---------------+-+ | | ||<br /> | |11 1 2 Asynchronous ---------------+-' | | ||<br /> | |Parity (0 - ignore parity bit) -----------------' | ||<br /> | |Parity (0 - odd parity,1 - even) -----------------' ||<br /> | |Unused ---------------------------------------------'|<br /> $FFFAAB|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |Buffer full --------------------------' | | | | | | ||<br /> | |Overrun error --------------------------' | | | | | ||<br /> | |Parity error -----------------------------' | | | | ||<br /> | |Frame error --------------------------------' | | | ||<br /> | |Found - Search/Break detected ----------------' | | ||<br /> | |Match/Character in progress --------------------' | ||<br /> | |Synchronous strip enable -------------------------' ||<br /> | |Receiver enable bit --------------------------------'|<br /> $FFFAAD|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W (TT)<br /> | |Buffer empty -------------------------' | | | | | | ||<br /> | |Underrun error -------------------------' | | | | | ||<br /> | |Auto turnaround --------------------------' | | | | ||<br /> | |End of transmission ------------------------' | | | ||<br /> | |Break ----------------------------------------' | | ||<br /> | |High bit ---------------------------------------' | ||<br /> | |Low bit ------------------------------------------' ||<br /> | |Transmitter enable ---------------------------------'|<br /> $FFFAAF|byte |USART data |R/W (TT)<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############6850 ACIA I/O Chips ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFC00|byte |Keyboard ACIA control BIT 7 6 5 4 3 2 1 0|W<br /> | |Rx Int enable (1 - enable) -----------' | | | | | | ||<br /> | |Tx Interrupts | | | | | | ||<br /> | |00 - RTS low, Tx int disable -----------+-+ | | | | ||<br /> | |01 - RTS low, Tx int enable ------------+-+ | | | | ||<br /> | |10 - RTS high, Tx int disable ----------+-+ | | | | ||<br /> | |11 - RTS low, Tx int disable, | | | | | | ||<br /> | | Tx a break onto data out ----------+-' | | | | ||<br /> | |Settings | | | | ||<br /> | |000 - 7 bit, even, 2 stop bit --------------+-+-+ | ||<br /> | |001 - 7 bit, odd, 2 stop bit ---------------+-+-+ | ||<br /> | |010 - 7 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |011 - 7 bit, odd, 1 stop bit ---------------+-+-+ | ||<br /> | |100 - 8 bit, 2 stop bit --------------------+-+-+ | ||<br /> | |101 - 8 bit, 1 stop bit --------------------+-+-+ | ||<br /> | |110 - 8 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |111 - 8 bit, odd, 1 stop bit ---------------+-+-' | ||<br /> | |Clock divide | ||<br /> | |00 - Normal --------------------------------------+-+|<br /> | |01 - Div by 16 -----------------------------------+-+|<br /> | |10 - Div by 64 -----------------------------------+-+|<br /> | |11 - Master reset --------------------------------+-'|<br /> $FFFC00|byte |Keyboard ACIA control BIT 7 6 5 4 3 2 1 0|R<br /> | |Interrupt request --------------------' | | | | | | ||<br /> | |Parity error ---------------------------' | | | | | ||<br /> | |Rx overrun -------------------------------' | | | | ||<br /> | |Framing error ------------------------------' | | | ||<br /> | |CTS ------------------------------------------' | | ||<br /> | |DCD --------------------------------------------' | ||<br /> | |Tx data register empty ---------------------------' ||<br /> | |Rx data register full ------------------------------'|<br /> $FFFC02|byte |Keyboard ACIA data |R/W<br /> $FFFC04|byte |MIDI ACIA control BIT 7 6 5 4 3 2 1 0|W<br /> | |Rx Int enable (1 - enable) -----------' | | | | | | ||<br /> | |Tx Interrupts | | | | | | ||<br /> | |00 - RTS low, Tx int disable -----------+-+ | | | | ||<br /> | |01 - RTS low, Tx int enable ------------+-+ | | | | ||<br /> | |10 - RTS high, Tx int disable ----------+-+ | | | | ||<br /> | |11 - RTS low, Tx int disable, | | | | | | ||<br /> | | Tx a break onto data out ----------+-' | | | | ||<br /> | |Settings | | | | ||<br /> | |000 - 7 bit, even, 2 stop bit --------------+-+-+ | ||<br /> | |001 - 7 bit, odd, 2 stop bit ---------------+-+-+ | ||<br /> | |010 - 7 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |011 - 7 bit, odd, 1 stop bit ---------------+-+-+ | ||<br /> | |100 - 8 bit, 2 stop bit --------------------+-+-+ | ||<br /> | |101 - 8 bit, 1 stop bit --------------------+-+-+ | ||<br /> | |110 - 8 bit, even, 1 stop bit --------------+-+-+ | ||<br /> | |111 - 8 bit, odd, 1 stop bit ---------------+-+-' | ||<br /> | |Clock divide | ||<br /> | |00 - Normal --------------------------------------+-+|<br /> | |01 - Div by 16 -----------------------------------+-+|<br /> | |10 - Div by 64 -----------------------------------+-+|<br /> | |11 - Master reset --------------------------------+-'|<br /> $FFFC04|byte |MIDI ACIA control BIT 7 6 5 4 3 2 1 0|R<br /> | |Interrupt request --------------------' | | | | | | ||<br /> | |Parity error ---------------------------' | | | | | ||<br /> | |Rx overrun -------------------------------' | | | | ||<br /> | |Framing error ------------------------------' | | | ||<br /> | |CTS ------------------------------------------' | | ||<br /> | |DCD --------------------------------------------' | ||<br /> | |Tx data register empty ---------------------------' ||<br /> | |Rx data register full ------------------------------'|<br /> $FFFC06|byte |MIDI ACIA data |R/W<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############Realtime Clock ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FFFC21|byte |S_Units |???<br /> $FFFC23|byte |S_Tens |???<br /> $FFFC25|byte |M_Units |???<br /> $FFFC27|byte |M_Tens |???<br /> $FFFC29|byte |H_Units |???<br /> $FFFC2B|byte |H_Tens |???<br /> $FFFC2D|byte |Weekday |???<br /> $FFFC2F|byte |Day_Units |???<br /> $FFFC31|byte |Day_Tens |???<br /> $FFFC33|byte |Mon_Units |???<br /> $FFFC35|byte |Mon_Tens |???<br /> $FFFC37|byte |Yr_Units |???<br /> $FFFC39|byte |Yr_Tens |???<br /> $FFFC3B|byte |Cl_Mod |???<br /> $FFFC3D|byte |Cl_Test |???<br /> $FFFC3F|byte |Cl_Reset |???<br /> -------+-----+-----------------------------------------------------+----------<br /> ##############ROM ###########<br /> -------+-----+-----------------------------------------------------+----------<br /> $FA0000| | |<br /> : | |128K ROM expansion cartridge port |R<br /> $FBFFFF| | |<br /> -------+-----+-----------------------------------------------------+----------<br /> $FC0000| | |<br /> : | |192K System ROM |R<br /> $FEFFFF| | |<br /> -------+-----+-----------------------------------------------------+----------<br /> <br /> Atari 32 bit Memory Map<br /> <br /> Addresses Description<br /> -------------------+----------------------------------------------------------<br /> $00000000-$00DFFFFF|ST RAM<br /> $00E00000-$00EFFFFF|512k TOS ROMs<br /> $00F00000-$00F9FFFF|Reserved I/O Space<br /> $00FA0000-$00FBFFFF|128k ROM cartridge expansion port<br /> $00FC0000-$00FEFFFF|192k System ROM<br /> $00FF0000-$00FF7FFF|Reserved I/O Space<br /> $00FF8000-$00FFFFFF|ST/TT I/O<br /> $01000000-$013FFFFF|TT Fast Ram<br /> $01400000-$FDFFFFFF|Reserved<br /> $FE000000-$FEFFFFFF|VME A24/D16<br /> $FEFF0000-$FEFFFFFF|VME A16/D16<br /> $FF000000-$FFFFFFFF|ST 24 bit compatible shadow<br /> $FFD000xx-$FFD000xx|Set FastRAM refresh rate and generate a bus error<br /> -------------------+----------------------------------------------------------<br /> <br /> Cookie Jar<br /> Atari &quot;Official&quot; Cookies<br /> Cookie Description<br /> -------+----------------------------------------------------------------------<br /> _CPU | CPU Type Bit 7 6 5 4 3 2 1 0<br /> | Processor type is represented in decimal in the lowest byte.<br /> | (0 - 68000, 40 - 68040)<br /> -------+----------------------------------------------------------------------<br /> _VDO | Video Type BIT 17 16<br /> | Shifter Type | |<br /> | 00 - ST ---------------------------------------------------------+--+<br /> | 01 - STe --------------------------------------------------------+--+<br /> | 10 - TT ---------------------------------------------------------+--+<br /> | 11 - Falcon030 --------------------------------------------------+--'<br /> -------+----------------------------------------------------------------------<br /> _FDC | Floppy Drive Controller BIT 25 24 . 23-0<br /> | Floppy Format | | |<br /> | 00 - DD (Normal floppy interface) ------------------------+--+ |<br /> | 01 - HD (1.44 MB with 3.5&quot;) ------------------------------+--+ |<br /> | 10 - ED (2.88 MB with 3.5&quot;) ------------------------------+--' |<br /> | Controller ID |<br /> | 0 - No information available |<br /> | 'ATC' - Fully compatible interface built in a way that -------------+<br /> | behaves like part of the system. |<br /> | 'DP1' - &quot;DreamPark Development&quot;, all ID's beginning with -----------'<br /> | &quot;DP&quot; are reserved for Dreampark.<br /> -------+----------------------------------------------------------------------<br /> _FLK | File Locking<br /> | If present, GEMDOS supports file locking. Value represents version<br /> | number of the expansion.<br /> -------+----------------------------------------------------------------------<br /> _NET | Network Type<br /> | If present, there is GEMDOS network support. Points to 2 longs:<br /> | The first is the ID of the producer, and the second is the version<br /> | number.<br /> -------+----------------------------------------------------------------------<br /> _SLM | SLM Driver<br /> | Diablo-driver for the SLM laser printer. Value points to a<br /> | non-documented structure.<br /> -------+----------------------------------------------------------------------<br /> _INF | .INF Patch<br /> | When present, STEFIX (patch program for TOS 1.06) is active.<br /> -------+----------------------------------------------------------------------<br /> _SND | Sound Hardware BIT 5 4 3 2 1 0<br /> | CodeC (??) -----------------------------------------------' | | | | |<br /> | Connection Matrix ------------------------------------------' | | | |<br /> | DSP56001 -----------------------------------------------------' | | |<br /> | 16 Bit DMA Sound -----------------------------------------------' | |<br /> | 8 Bit DMA Sound --------------------------------------------------' |<br /> | YM2149 -------------------------------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> _MCH | Machine Type BIT 17 16<br /> | 00 - ST/Mega ST -------------------------------------------------+--+<br /> | 01 - STe &amp; Compatible Machines (See Below) ----------------------+--+<br /> | 10 - TT ---------------------------------------------------------+--+<br /> | 11 - Falcon030 --------------------------------------------------+--'<br /> | STe &amp; Compatible Machines BIT 5 4 3 2 1 0<br /> | 00000 - STe ----------------------------------------------+-+-+-+-+-+<br /> | 00001 - ST Book ------------------------------------------+-+-+-+-+-+<br /> | 10000 - Mega STe -----------------------------------------+-+-+-+-+-'<br /> -------+----------------------------------------------------------------------<br /> _SWI | Configuration Switches<br /> | State of configuration switches (MSTe/TT only)<br /> -------+----------------------------------------------------------------------<br /> _FRB | Fast Ram Buffer<br /> | (TT specific) 64k buffer for ACSI DMA<br /> | 0 - no buffers assigned Not 0 - address of FastRam buffer<br /> -------+----------------------------------------------------------------------<br /> _FPU | FPU Type<br /> | Software FPU BIT 3 2 1 0<br /> | 68040's internal FPU -----------------------------------------' | | |<br /> | 01 - 6888x present ---------------------------------------------+-+ |<br /> | 10 - 68881 for sure --------------------------------------------+-+ |<br /> | 11 - 68882 for sure --------------------------------------------+-' |<br /> | SFP004 present -----------------------------------------------------'<br /> | Hardware FPU BIT 11 10 9 8<br /> | 68040's internal FPU ----------------------------------------' | | |<br /> | 01 - 6888x present ---------------------------------------------+-+ |<br /> | 10 - 68881 for sure --------------------------------------------+-+ |<br /> | 11 - 68882 for sure --------------------------------------------+-' |<br /> | SFP004 present -----------------------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> _OOL | PoolFix<br /> | Value corresponds to PoolFix version<br /> -------+----------------------------------------------------------------------<br /> _AKP | Keyboard/Language Configuration<br /> | Keyboard Configuration Bit 15-8<br /> | 1 - German 5 - Italian -------------------------------------------+<br /> | 2 - French 7 - Swiss French --------------------------------------+<br /> | 4 - Spanish 8 - Swiss German --------------------------------------+<br /> | All others - English -----------------------------------------------'<br /> | Language Configuration BIT 7-0<br /> | 1 - German 5 - Italian -------------------------------------------+<br /> | 2 - French 7 - Swiss French --------------------------------------+<br /> | 4 - Spanish 8 - Swiss German --------------------------------------+<br /> | All others - English -----------------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> _IDT | International Date/Time Format<br /> | Time Format BIT 12<br /> | 0 - AM/PM, 1 - 24 hours --------------------------------------------+<br /> | Date Format BIT 9 8<br /> | 00 - MMDDYY ------------------------------------------------------+-+<br /> | 01 - DDMMYY ------------------------------------------------------+-+<br /> | 10 - YYMMDD ------------------------------------------------------+-+<br /> | 11 - YYDDMM ------------------------------------------------------+-'<br /> | Separator for date BIT 7-0<br /> | ASCII Value (i.e. &quot;.&quot; or &quot;/&quot;) --------------------------------------'<br /> -------+----------------------------------------------------------------------<br /> MiNT | MiNT<br /> | Present if MiNT/MultiTOS is active. Value represents the version<br /> | number of the MiNT kernel in hex (0x104 = 1.04)<br /> -------+----------------------------------------------------------------------<br /> &lt;/pre&gt;<br /> <br /> [[Category:Programming]]<br /> [[Category:Memory Address]]</div>

Cyprian