ST STE Scanlines - Revision history

AtariWikiSysop: 20 revisions imported

2018-06-03T23:13:19Z

20 revisions imported

Troed: /* Horizontal GST MCU state machine, STE */

2016-04-11T21:26:47Z

‎Horizontal GST MCU state machine, STE

Troed: Major update for ST and STE GLUE horizontal tables. Previously they were correct for 50Hz lines, now 60Hz also.

2016-04-11T21:19:55Z

Major update for ST and STE GLUE horizontal tables. Previously they were correct for 50Hz lines, now 60Hz also.

Show changes

Larsbrinkhoff: /* Shifter state machine */ RR always shift out pixels, whether DE is active or not.

2016-03-29T08:29:40Z

‎Shifter state machine: RR always shift out pixels, whether DE is active or not.

Troed at 14:22, 27 March 2016

2016-03-27T14:22:21Z

Troed: /* Shifter state machine */

2016-03-25T22:44:17Z

‎Shifter state machine

Troed: /* Shifter state machine */ first comment on how it works, based on "every other 16 pixels" hypothesis

2016-03-25T17:51:58Z

‎Shifter state machine: first comment on how it works, based on "every other 16 pixels" hypothesis

Troed: Changed == LO to != HI as per Alien's comment on A-F

2016-03-17T01:57:07Z

Changed == LO to != HI as per Alien's comment on A-F

Troed: Added vertical statemachine

2016-03-17T01:09:07Z

Added vertical statemachine

Troed at 23:25, 30 January 2014

2014-01-30T23:25:02Z

@@ Line 154: / Line 154: @@
 |-
 |0
-|IF(RES == HI) PRELOAD = TRUE
+|IF(71) PRELOAD = TRUE
 |-
 |24

@@ Line 289: / Line 289: @@
 '''Work in progress. Please read through Alien's articles first for terminology. This writeup will be expanded upon in time, and likely contains severe errors.'''
-The Shifter has two types of registers. A four word FIFO buffer ("IR" in Alien's articles) and four words used as shift-registers ("RR") that are shifted out every cycle together with a palette lookup that sets the correct value on the RGB/Mono pins. When Shifter receives LOAD from the MMU it will read a word to the FIFO. As long as DE is active the shift-registers will continuously shift out data. In low resolution all four words shift together, in medium resolution two of them shift together and in high resolution one shift at a time. Every 16 cycles a check is made to see whether the FIFO is full and the contents will then be copied to RR.
+The Shifter has two types of registers. A four word FIFO buffer ("IR" in Alien's articles) and four words used as shift-registers ("RR") that are shifted out every cycle together with a palette lookup that sets the correct value on the RGB/Mono pins. When Shifter receives LOAD from the MMU it will read a word to the FIFO. The shift-registers are constantly shifting out data. In low resolution all four words shift together, in medium resolution two of them shift together and in high resolution one shift at a time. Every 16 cycles a check is made to see whether the FIFO is full and the contents will then be copied to RR.  If DE is not active, LOAD will not be asserted, the FIFO will not be refilled, and RR will not be updated. When RR is not updated with new data, the registers will be 0, and the border color will be displayed.
 The concept of a FIFO is hypothesized to be the explanation for "every other 16 pixels black", a Shifters substate that in reality is border color (palette 0), and is only "every other" in low resolution. In high resolution it's every fifth group of 16 pixels. The cause is speculated to be that sometimes the copy from IR to RR simply fails. This will cause all zeros (palette 0) to be shifted out for 16 cycles. Since the next group of 16 pixels are displayed in the correct position one word must've been pushed out from the FIFO and the next have been added correctly.

@@ Line 15: / Line 15: @@
-== Horisontal GLUE state machine, ST ==
+== Horizontal GLUE state machine, ST ==
 Due to lack of synchronisation between GLUE and CPU when an ST is powered on both chips, while running at 8MHz, can be offset from each other. This is the hypothesised cause behind what's known as ST "wakeup modes" (where two were known and documented beginning 2006 [http://www.atari-forum.com/viewtopic.php?f=68&t=9527&start=34]) and more recently divided into two more making four in total, now known as "wakestates" (2013) [http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=147].
@@ Line 126: / Line 126: @@
 * Cycle 380, GLUE lowered DE. MMU will no longer raise LOAD from cycle 384
-== Horisontal GST MCU state machine, STE ==
+== Horizontal GST MCU state machine, STE ==
 In the STE the GLUE and MMU were combined into a single circuit, the GST MCU. This also meant that the GLUE and CPU were no longer offset by 0-3 cycles as on the ST but fully synchronised at 0. Thus there are no GLUE wakeup modes/wakestates known on the STE. Several changes were however made to accommodate hardware scroll support where one of the more notable ones was an earlier check for starting the screen in high res (= left border) which caused many older border removing demos to fail.

@@ Line 291: / Line 291: @@
 The Shifter has two types of registers. A four word FIFO buffer ("IR" in Alien's articles) and four words used as shift-registers ("RR") that are shifted out every cycle together with a palette lookup that sets the correct value on the RGB/Mono pins. When Shifter receives LOAD from the MMU it will read a word to the FIFO. As long as DE is active the shift-registers will continuously shift out data. In low resolution all four words shift together, in medium resolution two of them shift together and in high resolution one shift at a time. Every 16 cycles a check is made to see whether the FIFO is full and the contents will then be copied to RR.
-The concept of a FIFO is hypothesized to be the explanation for "every other 16 pixels black", a Shifters substate that in reality is border color (palette 0), and is only "every other" in low resolution. In high resolution it's every fifth group of 16 pixels. The cause is speculated to be that sometimes the copy from IR to RR simply fails. This will cause all zeros (palette 0) to be shifted out for 16 cycles. Since the next group of 16 pixels are displayed in the correct position one word must've been pushed out and the next have been read correctly.
+The concept of a FIFO is hypothesized to be the explanation for "every other 16 pixels black", a Shifters substate that in reality is border color (palette 0), and is only "every other" in low resolution. In high resolution it's every fifth group of 16 pixels. The cause is speculated to be that sometimes the copy from IR to RR simply fails. This will cause all zeros (palette 0) to be shifted out for 16 cycles. Since the next group of 16 pixels are displayed in the correct position one word must've been pushed out from the FIFO and the next have been added correctly.
 == Sync line lengths ==

@@ Line 285: / Line 285: @@
 == Shifter state machine ==
-TBD
+Regular sync scrolling is made with changes affecting GLUE. 4-pixel sync scrolling as well as the cause for "stable" and "unstable" sync lines is due to Shifter.
-Regular sync scrolling is made with changes affecting GLUE. 4-pixel sync scrolling as well as the cause for "stable" and "unstable" sync lines is due to Shifter.
+The concept of a FIFO is hypothesized to be the explanation for "every other 16 pixels black", a Shifters substate that in reality is border color (palette 0), and is only "every other" in low resolution. In high resolution it's every fifth group of 16 pixels. The cause is speculated to be that sometimes the copy from IR to RR simply fails. This will cause all zeros (palette 0) to be shifted out for 16 cycles. Since the next group of 16 pixels are displayed in the correct position one word must've been pushed out and the next have been read correctly.
 == Sync line lengths ==

← Older revision	Revision as of 23:13, 3 June 2018
(No difference)

@@ Line 49: / Line 49: @@
 |-
 |30
-|IF(RES == LO) BLANK = FALSE
+|IF(RES != HI) BLANK = FALSE
 |-
 |52
-|IF(FREQ == 60) && (RES == LO) H = TRUE
+|IF(FREQ == 60) && (RES != HI) H = TRUE
 |-
 |54
@@ Line 58: / Line 58: @@
 |-
 |56
-|IF(FREQ == 50) && (RES == LO) H = TRUE
+|IF(FREQ == 50) && (RES != HI) H = TRUE
 |-
 |164
@@ Line 67: / Line 67: @@
 |-
 |372
-|IF(FREQ == 60) && (RES == LO) H = FALSE
+|IF(FREQ == 60) && (RES != HI) H = FALSE
 |-
 |376
-|IF(FREQ == 50) && (RES == LO) H = FALSE
+|IF(FREQ == 50) && (RES != HI) H = FALSE
 |-
 |450
-|IF(RES == LO) BLANK = TRUE
+|IF(RES != HI) BLANK = TRUE
 |-
 |462
-|IF(RES == LO) HSYNC = TRUE && H = FALSE
+|IF(RES != HI) HSYNC = TRUE && H = FALSE
 |-
 |502
-|IF(RES == LO) HSYNC = FALSE
+|IF(RES != HI) HSYNC = FALSE
 |}
@@ Line 117: / Line 117: @@
 * 64-61 = 3 = DL3
-After LOAD it takes 16 cycles, plus 2 due to internal delays, for the Shifter to set the first values on the RGB pins. As long as DE is high LOAD will looping with new data available. For each word read by the Shifter the MMU will increase the video counter.
+After LOAD it takes 16 cycles, plus 2 due to internal delays, for the Shifter to set the first values on the RGB pins. As long as DE is high LOAD will loop with new data available. For each word read by the Shifter the MMU will increase the video counter.
 Note: These cycle timings are NOT affected by ST wake states
@@ Line 161: / Line 161: @@
 |-
 |28
-|IF(RES == LO) BLANK = FALSE
+|IF(RES != HI) BLANK = FALSE
 |-
 |36
-|IF(FREQ == 60) && (RES == LO) PRELOAD = TRUE
+|IF(FREQ == 60) && (RES != HI) PRELOAD = TRUE
 |-
 |40
-|IF(FREQ == 50) && (RES == LO) PRELOAD = TRUE
+|IF(FREQ == 50) && (RES != HI) PRELOAD = TRUE
 |-
 |56
@@ Line 182: / Line 182: @@
 |-
 |372
-|IF(FREQ == 60) && (RES == LO) H = FALSE
+|IF(FREQ == 60) && (RES != HI) H = FALSE
 |-
 |376
-|IF(FREQ == 50) && (RES == LO) H = FALSE
+|IF(FREQ == 50) && (RES != HI) H = FALSE
 |-
 |448
-|IF(RES == LO) BLANK = TRUE
+|IF(RES != HI) BLANK = TRUE
 |-
 |460
-|IF(RES == LO) HSYNC = TRUE && H = FALSE
+|IF(RES != HI) HSYNC = TRUE && H = FALSE
 |-
 |500
-|IF(RES == LO) HSYNC = FALSE
+|IF(RES != HI) HSYNC = FALSE
 |}

@@ Line 2: / Line 2: @@
 Disclaimer: This page has as a goal to contain everything that's currently known, but by no means it should be considered complete.
 Information used to create these tables has mostly been sourced from the people below, but a general thanks goes out to everyone who's ever written anything on the subject.
@@ Line 9: / Line 13: @@
 * Dio (posts on Atari-Forum, trace diagrams, DE-to-LOAD) [http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=363]
 * Troed of SYNC (GLUE-CPU wakestate hypothesis, STE pre-fetch impact) [http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=407]
 == GLUE state machine, ST ==