IU : Integer multiplication and division

Posted on 2014/04/18 by dev

First, there are two kinds of multipliers and dividers in our CPU, the integer and the floating point ones. They are a bit different.

Keyboard and Mouse

Posted on 2014/04/08 by dev

To complete our workstation, after the video output, we need a keyboard and, eventually, a mouse.

TCX

Posted on 2014/03/28 by dev

TEMLIB v3 now includes a video controller suitable for the Sun4m workstation.

TEMLIB r3

Posted on 2014/03/22 by dev

Adding Keyboard, Mouse, Video !

IU : Condition codes

Posted on 2013/12/22 by dev

SPARC CPUs use condition codes, the famous NZVC bits (Negative, Zero, ‘Verflow and Carry).

FIFOs, buffers, and pipelines

Posted on 2013/11/27 by dev

Things you ought to know!

IU : Pipelined : Multicycle

Posted on 2013/11/21 by dev

Some instructions last more than one cycle, even on RISC CPUs.

IU : Pipelined : Stall and Bypass

Posted on 2013/10/31 by dev

Integer registers are read at the beginning of the EXECUTE stage and are updated at the end of the WRITE stage.

IU : Pipelined : Traps

Posted on 2013/10/26 by dev

There are many circumstances where a CPU may halt and jump to an exception vector:

IU : Pipelined : PIPE5 presentation

Posted on 2013/10/15 by dev

This is the traditional RISC implementation, the one you find in hundreds of CPU cores, thousands of books, millions of computer architecture courses, gazillions chips.